mirror of
https://github.com/Azimer/Apollo.git
synced 2024-05-21 13:28:09 -04:00
285 lines
8.7 KiB
C++
285 lines
8.7 KiB
C++
#include <windows.h>
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#include <stdio.h>
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#include "WinMain.h"
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extern u8 *idmem;
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extern u8 *rdram;
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//#define rdram (char *)AudioInfo.RDRAM
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#define dmem idmem
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#define imem (u8 *)(idmem + 0x1000)
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char *rspreg[0x20] = {
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"R0", "AT", "V0", "V1", "A0", "A1", "A2", "A3", "T0", "T1", "T2",
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"T3", "T4", "T5", "T6", "T7", "S0", "S1", "S2", "S3", "S4", "S5",
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"S6", "S7", "T8", "T9", "K0", "K1", "GP", "SP", "S8", "RA"
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};
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int multi[0xC] = {
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0, 1, 2, 3, 4, 4, 3, 3, 4, 4, 4, 4
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};
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char *StoreVec[0xC] = {
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"SBV", "SSV", "SLV", "SDV", "SQV", "SRV", "SPV", "SUV", "SHV", "SFV", "SWV", "STV"
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};
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char *LoadVec[0xC] = {
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"LBV", "LSV", "LLV", "LDV", "LQV", "LRV", "LPV", "LUV", "LHV", "LFV", "LWV", "LTV"
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};
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char *Cop0Name[0x20] = {
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"SP memory address", "SP DRAM DMA address", "SP read DMA length", "SP write DMA length",
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"SP status", "SP DMA full", "SP DMA busy", "SP semaphore",
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"DP CMD DMA start", "DP CMD DMA end", "DP CMD DMA current", "DP CMD status",
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"DP clock counter", "DP buffer busy counter", "DP pipe busy counter", "DP TMEM load counter",
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"Unknown CPR0", "Unknown CPR0", "Unknown CPR0", "Unknown CPR0",
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"Unknown CPR0", "Unknown CPR0", "Unknown CPR0", "Unknown CPR0",
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"Unknown CPR0", "Unknown CPR0", "Unknown CPR0", "Unknown CPR0",
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"Unknown CPR0", "Unknown CPR0", "Unknown CPR0", "Unknown CPR0"
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};
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#define _RS ((opcode >> 21) & 0x1f)
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#define _RT ((opcode >> 16) & 0x1f)
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#define _RD ((opcode >> 11) & 0x1f)
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#define _SA ((opcode >> 06) & 0x1f)
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#define _IMM ((opcode & 0xFFFF))
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#define _FUNC ((opcode & 0x3F))
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char *LoadStoreOp [0xC] = {
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"LB", "LH", "??", "LW", "LBU", "LHU", "??", "??",
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"SB", "SH", "??", "SW"
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};
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char *Space (char *word) {
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static char retVal [9];
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int cnt;
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memset (retVal, 32, 8);
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retVal[8] = '\0';
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cnt = 0;
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while ((cnt < 8) && (word[cnt] != '\0')) {
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retVal[cnt] = word[cnt];
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cnt++;
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}
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return retVal;
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}
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char *VectOp [0x40] = {
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"VMULF", "VMULU", "VRNDP", "VMULQ", "VMUDL", "VMUDM", "VMUDN", "VMUDH",
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"VMACF", "VMACU", "VRNDN", "VMACQ", "VMADL", "VMADM", "VMADN", "VMADH",
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"VADD ", "VSUB ", "?????", "VABS ", "VADDC", "VSUBC", "?????", "?????",
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"?????", "?????", "?????", "?????", "?????", "VSAW ", "?????", "?????",
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"VLT ", "VEQ ", "VNE ", "VGE ", "VCL ", "VCH ", "VCR ", "VMRG ",
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"VAND ", "VNAND", "VOR ", "VNOR ", "VXOR ", "VNXOR", "?????", "?????",
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"VRCP ", "VRCPL", "VRCPH", "VMOV ", "VRSQ ", "VRSQL", "VRSQH", "VNOOP",
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"?????", "?????", "?????", "?????", "?????", "?????", "?????", "?????",
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};
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char *SHIFTS[0x8] = {
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"SLL", "", "SRL", "SRA", "SLLV", "SRLV", "SRLV", "SRAV"
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};
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char *LOGICS[0xC] = {
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"ADD", "ADDU", "SUB", "SUBU", "AND", "OR", "XOR", "NOR",
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"", "", "SLT", "SLTU"
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};
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char *ElemSpec[0x10] = {
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"", "", "[0q]", "[1q]", "[0h]", "[1h]", "[2h]", "[3h]",
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"[0]", "[1]", "[2]", "[3]", "[4]", "[5]", "[6]", "[7]"
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};
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void DumpRSPLine(char *buffer, DWORD sppc) {
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DWORD opcode;
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buffer[0] = '\0';
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opcode = *(DWORD *)(imem+(sppc&0xFFF));
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sprintf (buffer, "0x%04X %08X", sppc&0xFFFF, opcode);
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buffer += 8;
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switch ((opcode >> 26)) {
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case 0x0: // NOOP
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switch (_FUNC) {
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case 0x0: // SLL/NOP
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if (_RD == 0) {
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sprintf (buffer, "NOP");
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break;
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}
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case 0x2: // SRL
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case 0x3: // SRA
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case 0x4: // SLLV
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case 0x6: // SRLV
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case 0x7: // SRAV
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sprintf (buffer, "%s %s, %s, 0x%02X", Space (SHIFTS[_FUNC]), rspreg[_RD], rspreg[_RT], _SA);
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break;
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case 0x8: // JR
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sprintf (buffer, "%s %s", Space ("JR"), rspreg[_RS]);
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break;
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case 0x9: // JALR
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sprintf (buffer, "%s %s, %s", Space ("JALR"), rspreg[_RD], rspreg[_RS]);
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break;
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case 0xD: // BREAK
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sprintf (buffer, "%s", Space ("BREAK"));
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break;
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case 0x20: // ADD
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if (_RS == 0)
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sprintf (buffer, "%s %s, %s", Space ("MOVE"), rspreg[_RD], rspreg[_RT]);
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else if (_RT == 0)
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sprintf (buffer, "%s %s, %s", Space ("MOVE"), rspreg[_RD], rspreg[_RS]);
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else
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sprintf (buffer, "%s %s, %s, %s", Space ("ADD"), rspreg[_RD], rspreg[_RS], rspreg[_RT]);
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break;
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case 0x21: // ADDU
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case 0x22: // SUB
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case 0x23: // SUBU
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case 0x24: // AND
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case 0x25: // OR
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case 0x26: // XOR
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case 0x27: // NOR
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case 0x2A: // SLT
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case 0x2B: // SLTU
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sprintf (buffer, "%s %s, %s, %s", Space (LOGICS[_FUNC-0x20]), rspreg[_RD], rspreg[_RS], rspreg[_RT]);
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break;
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}
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break;
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case 0x1: // REG IMM
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switch (_RT) {
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case 0x00: // BLTZ
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sprintf (buffer, "%s %s, 0x%04X", Space ("BLTZ"), rspreg[_RS], ((_IMM << 2)+sppc+4)&0xFFFF);
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break;
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case 0x01: // BGEZ
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sprintf (buffer, "%s %s, 0x%04X", Space ("BGEZ"), rspreg[_RS], ((_IMM << 2)+sppc+4)&0xFFFF);
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break;
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case 0x10: // BLTZAL
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sprintf (buffer, "%s %s, 0x%04X", Space ("BLTZAL"), rspreg[_RS], ((_IMM << 2)+sppc+4)&0xFFFF);
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break;
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case 0x11: // BGEZAL
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sprintf (buffer, "%s %s, 0x%04X", Space ("BGEZAL"), rspreg[_RS], ((_IMM << 2)+sppc+4)&0xFFFF);
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break;
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}
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break;
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case 0x2: // J
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sprintf (buffer, "%s 0x%04X", Space("J"), ((_IMM << 2) & 0xFFFF));
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break;
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case 0x3: // JAL
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sprintf (buffer, "%s 0x%04X", Space("JAL"), ((_IMM << 2) & 0xFFFF));
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break;
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case 0x4: // BEQ
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if (_RT == 0) {
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sprintf (buffer, "%s %s, 0x%04X", Space ("BEQZ"), rspreg[_RS], ((_IMM << 2)+sppc+4)&0xFFFF);
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} else if (_RS == 0) {
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sprintf (buffer, "%s %s, 0x%04X", Space ("BEQZ"), rspreg[_RT], ((_IMM << 2)+sppc+4)&0xFFFF);
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} else {
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sprintf (buffer, "%s %s, %s, 0x%04X", Space ("BEQ"), rspreg[_RS], rspreg[_RT], ((_IMM << 2)+sppc+4)&0xFFFF);
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}
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break;
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case 0x5: // BNE
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if (_RT == 0) {
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sprintf (buffer, "%s %s, 0x%04X", Space ("BNEZ"), rspreg[_RS], ((_IMM << 2)+sppc+4)&0xFFFF);
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} else if (_RS == 0) {
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sprintf (buffer, "%s %s, 0x%04X", Space ("BNEZ"), rspreg[_RT], ((_IMM << 2)+sppc+4)&0xFFFF);
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} else {
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sprintf (buffer, "%s %s, %s, 0x%04X", Space ("BNE"), rspreg[_RS], rspreg[_RT], ((_IMM << 2)+sppc+4)&0xFFFF);
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}
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break;
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case 0x6: // BLEZ
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sprintf (buffer, "%s %s, 0x%04X", Space ("BLEZ"), rspreg[_RS], ((_IMM << 2)+sppc+4)&0xFFFF);
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break;
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break;
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case 0x7: // BGTZ
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sprintf (buffer, "%s %s, 0x%04X", Space ("BGTZ"), rspreg[_RS], ((_IMM << 2)+sppc+4)&0xFFFF);
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break;
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case 0x8: // ADDI
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sprintf (buffer, "%s %s, %s, 0x%04X", Space("ADDI"), rspreg[_RT], rspreg[_RS], _IMM);
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break;
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case 0xC: // ANDI
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sprintf (buffer, "%s %s, %s, 0x%04X", Space("ANDI"), rspreg[_RT], rspreg[_RS], _IMM);
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break;
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case 0xD: // ORI
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sprintf (buffer, "%s %s, %s, 0x%04X", Space("ORI"), rspreg[_RT], rspreg[_RS], _IMM);
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break;
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case 0xF: // LUI
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sprintf (buffer, "%s %s, 0x%04X", Space("LUI"), rspreg[_RT], _IMM);
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break;
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case 0x10: // COP0
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switch (_RS) {
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case 0x00: // MFC0
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sprintf (buffer, "%s %s, %s", Space("MFC0"), rspreg[_RT], Cop0Name[_RD]);
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break;
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case 0x04: // MTC0
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sprintf (buffer, "%s %s, %s", Space("MTC0"), rspreg[_RT], Cop0Name[_RD]);
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break;
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}
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break;
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case 0x12: // RSP Vector Ops
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if (_RS < 0x10) {
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switch (_RS) {
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case 0x00: // MFC2
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sprintf (buffer, "%s %s, $v%i [%i]", Space("MFC2"), rspreg[_RT], _RD, ((_SA >> 1) & 0xF));
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break;
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case 0x02: // CFC2
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sprintf (buffer, "%s %s, %i", Space("CFC2"), rspreg[_RT], (_RD & 0x3));
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break;
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case 0x04: // MTC2
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sprintf (buffer, "%s %s, $v%i [%i]", Space("MFC2"), rspreg[_RT], _RD, ((_SA >> 1) & 0xF));
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break;
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case 0x06: // CTC2
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sprintf (buffer, "%s %s, %i", Space("CTC2"), rspreg[_RT], (_RD & 0x3));
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break;
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}
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} else {
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if (VectOp[_FUNC][0] != '?') {
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sprintf (buffer, "%s $v%i, $v%i, $v%i %s", Space (VectOp[_FUNC]), _SA, _RD, _RT, ElemSpec[_RS&0xF]);
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}
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}
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break;
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case 0x20: // LB
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case 0x21: // LH
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case 0x23: // LW
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case 0x24: // LBU
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case 0x25: // LBH
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case 0x28: // SB
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case 0x29: // SH
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case 0x2B: // SW
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sprintf (buffer, "%s %s, 0x%04X (%s)", Space(LoadStoreOp[(opcode>>26)-0x20]), rspreg[_RT], _IMM, rspreg[_RS]);
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break;
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case 0x32: // LWC2
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sprintf (buffer, "%s $v%i [%i], 0x%04X (%s)", Space(LoadVec[_RD]), _RT, ((_SA>>1)&0xF), (_FUNC << multi[_RD]), rspreg[_RS]);
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break;
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case 0x3A: // SWC2
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sprintf (buffer, "%s $v%i [%i], 0x%04X (%s)", Space(StoreVec[_RD]), _RT, ((_SA>>1)&0xF), (_FUNC << multi[_RD]), rspreg[_RS]);
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break;
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default:
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break;
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}
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}
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void RspDump () {
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FILE *output;
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char Buffer[256];
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FILE *dfile;
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int i;
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u8 *dm = (u8 *)dmem;
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char str[0x10];
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dfile = fopen ("c:\\audio.txt", "wt");
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output = fopen ("c:\\rspdump.txt", "wt");
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for (DWORD sppc = 0xA4001000; sppc < 0xA4002000; sppc+=4) {
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DumpRSPLine(Buffer, sppc);
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strcat (Buffer, "\n");
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fprintf (output, Buffer);
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}
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fclose (output);
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for (i=0; i < 0x1000; i++) {
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if ((i & 0xF) == 0x0)
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fprintf (dfile, "%04X: ", i);
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fprintf (dfile, "%02X ", dm[i^3]);
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str[i&0xf] = dm[i^3];
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if ((i & 0xF) == 0xF)
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fprintf (dfile, "\n", str);
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}
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fclose (dfile);
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Debug (0, "Dumped RSP");
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//__asm int 3;
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} |