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MIPS requires 2-byte reads to be aligned to even addresses. #define FAST_ALIGNED_LSB_WORD_ACCESS and use it to read absolute 24-bit addresses as either 1 byte & 1 halfword, or 1 halfword & 1 byte.

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This commit is contained in:
Nebuleon Fumika 2012-12-31 13:46:47 -05:00
parent 22fa90a3b3
commit c5d385d664
2 changed files with 15 additions and 0 deletions
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10
source/cpuaddr.h
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@ -256,6 +256,11 @@ static void AbsoluteLong (AccessMode a, InternalOp op)
long Addr;
#ifdef FAST_LSB_WORD_ACCESS
Addr = (*(uint32 *) CPU.PC) & 0xffffff;
#elif defined FAST_ALIGNED_LSB_WORD_ACCESS
if (((int) CPU.PC & 1) == 0)
Addr = (*(uint16 *) CPU.PC) + (*(CPU.PC + 2) << 16);
else
Addr = *CPU.PC + ((*(uint16 *) (CPU.PC + 1)) << 8);
#else
Addr = *CPU.PC + (*(CPU.PC + 1) << 8) + (*(CPU.PC + 2) << 16);
#endif
@ -434,6 +439,11 @@ static void AbsoluteLongIndexedX (AccessMode a, InternalOp op)
long Addr;
#ifdef FAST_LSB_WORD_ACCESS
Addr = (*(uint32 *) CPU.PC + ICPU.Registers.X.W) & 0xffffff;
#elif defined FAST_ALIGNED_LSB_WORD_ACCESS
if (((int) CPU.PC & 1) == 0)
Addr = ((*(uint16 *) CPU.PC) + (*(CPU.PC + 2) << 16) + ICPU.Registers.X.W) & 0xFFFFFF;
else
Addr = (*CPU.PC + ((*(uint16 *) (CPU.PC + 1)) << 8) + ICPU.Registers.X.W) & 0xFFFFFF;
#else
Addr = (*CPU.PC + (*(CPU.PC + 1) << 8) + (*(CPU.PC + 2) << 16) + ICPU.Registers.X.W) & 0xffffff;
#endif

5
source/port.h
View file

@ -274,6 +274,11 @@ EXTERN_C void MixSound(void);
defined(__WIN32__) || defined(__alpha__)
#define LSB_FIRST
#define FAST_LSB_WORD_ACCESS
#elif defined(__MIPSEL__)
#define LSB_FIRST
// On little-endian MIPS, a 16-bit word can be read directly from an address
// only if it's aligned.
#define FAST_ALIGNED_LSB_WORD_ACCESS
#else
//#define MSB_FIRST
#define LSB_FIRST