mirror of
https://github.com/liuk7071/ChonkyStation.git
synced 2024-06-01 10:47:56 -04:00
311 lines
10 KiB
C++
311 lines
10 KiB
C++
#include <memory.hpp>
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Memory::Memory(Interrupt* interrupt, DMA* dma, GPU* gpu, CDROM* cdrom) : interrupt(interrupt), dma(dma), gpu(gpu), cdrom(cdrom) {
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std::memset(ram, 0, 2_MB);
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std::memset(scratchpad, 0, 1_KB);
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readTable.resize(0x10000, 0);
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writeTable.resize(0x10000, 0);
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constexpr u32 PAGE_SIZE = 64_KB; // Page size = 64KB
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#ifndef ENABLE_RAM_MIRRORING
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constexpr auto ramPages = 32;
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#else
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constexpr auto ramPages = 32 * 4;
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#endif
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for (auto pageIndex = 0; pageIndex < ramPages; pageIndex++) {
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const auto pointer = (uintptr_t)&ram[(pageIndex * PAGE_SIZE) & 0x1FFFFF];
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readTable[pageIndex + 0x0000] = pointer; // KUSEG RAM
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readTable[pageIndex + 0x8000] = pointer; // KSEG0
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readTable[pageIndex + 0xA000] = pointer; // KSEG1
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writeTable[pageIndex + 0x0000] = pointer; // KUSEG RAM
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writeTable[pageIndex + 0x8000] = pointer; // KSEG0
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writeTable[pageIndex + 0xA000] = pointer; // KSEG1
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}
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for (auto pageIndex = 0; pageIndex < 8; pageIndex++) {
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const auto pointer = (uintptr_t)&bios[(pageIndex * PAGE_SIZE)];
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readTable[pageIndex + 0x1FC0] = pointer; // KUSEG
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readTable[pageIndex + 0x9FC0] = pointer; // KSEG0
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readTable[pageIndex + 0xBFC0] = pointer; // KSEG1
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}
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}
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void Memory::loadBios(const fs::path& biosPath) {
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auto temp = Helpers::readBinary(biosPath);
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std::memcpy(bios, temp.data(), 512_KB);
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}
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u32 Memory::maskAddress(u32 vaddr) {
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static const u32 ADDR_MASK[] = {
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0x7FFFFFFF,
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0x1FFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF
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};
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const auto idx = (vaddr >> 29);
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return vaddr & ADDR_MASK[idx];
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}
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template<>
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u8 Memory::read(u32 vaddr) {
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const auto page = vaddr >> 16;
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const auto pointer = readTable[page];
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// Use fast memory if the address is in the fastmem table
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if (pointer) {
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return *(u8*)(pointer + (vaddr & 0xffff));
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}
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u32 paddr = maskAddress(vaddr);
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if (Helpers::inRangeSized<u32>(paddr, 0x1f800000, 1_KB)) return scratchpad[paddr - 0x1f800000];
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// CDROM
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else if (paddr == 0x1f801800) return cdrom->readStatus();
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else if (paddr == 0x1f801801) {
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switch (cdrom->getIndex()) {
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case 1: return cdrom->getResponseByte();
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default:
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Helpers::panic("[ FATAL ] Unhandled CDROM read8 0x1f801801.%d", cdrom->getIndex());
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}
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}
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else if (paddr == 0x1f801803) {
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switch (cdrom->getIndex()) {
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case 1: return cdrom->readIF();
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default:
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Helpers::panic("[ FATAL ] Unhandled CDROM read8 0x1f801803.%d", cdrom->getIndex());
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}
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}
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// SIO
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else if (Helpers::inRangeSized<u32>(paddr, (u32)MemoryBase::SIO, (u32)MemorySize::SIO)) return 0;
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else if (Helpers::inRangeSized<u32>(paddr, 0x1f000000, 0x400)) return 0xff;
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else
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Helpers::panic("[ FATAL ] Unhandled read8 0x%08x (virtual 0x%08x)\n", paddr, vaddr);
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}
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template<>
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u16 Memory::read(u32 vaddr) {
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const auto page = vaddr >> 16;
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const auto pointer = readTable[page];
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// Use fast memory if the address is in the fastmem table
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if (pointer) {
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return *(u16*)(pointer + (vaddr & 0xffff));
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}
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u32 paddr = maskAddress(vaddr);
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// Scratchpad
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if (Helpers::inRangeSized<u32>(paddr, 0x1f800000, 1_KB)) {
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u32 data = 0;
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std::memcpy(&data, &scratchpad[paddr - 0x1f800000], sizeof(u16));
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return data;
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}
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// Interrupt
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else if (paddr == 0x1f801070) return interrupt->readIstat();
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else if (paddr == 0x1f801074) return interrupt->readImask();
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// SIO
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else if (Helpers::inRangeSized<u32>(paddr, (u32)MemoryBase::SIO, (u32)MemorySize::SIO)) return 0;
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// SPU
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else if (Helpers::inRangeSized<u32>(paddr, (u32)MemoryBase::SPU, (u32)MemorySize::SPU)) return 0;
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else
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Helpers::panic("[ FATAL ] Unhandled read16 0x%08x (virtual 0x%08x)\n", paddr, vaddr);
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}
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template<>
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u32 Memory::read(u32 vaddr) {
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const auto page = vaddr >> 16;
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const auto pointer = readTable[page];
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// Use fast memory if the address is in the fastmem table
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if (pointer) {
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return *(u32*)(pointer + (vaddr & 0xffff));
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}
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u32 paddr = maskAddress(vaddr);
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// Scratchpad
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if (Helpers::inRangeSized<u32>(paddr, 0x1f800000, 1_KB)) {
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u32 data = 0;
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std::memcpy(&data, &scratchpad[paddr - 0x1f800000], sizeof(u32));
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return data;
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}
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// GPU
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else if (paddr == 0x1f801810) return gpu->gpuRead();
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else if (paddr == 0x1f801814) return gpu->getStat();
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// Interrupt
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else if (paddr == 0x1f801070) return interrupt->readIstat();
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else if (paddr == 0x1f801074) return interrupt->readImask();
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// DMA
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else if (Helpers::inRange<u32>(paddr, 0x1f801080, 0x1f8010e8)) {
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const auto channel = ((paddr >> 4) & 0xf) - 8;
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Helpers::debugAssert(channel < 7, "Tried to access %dth DMA channel", channel); // Should not get triggered
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switch (paddr & 0xf) {
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case 0x0: return dma->channels[channel].madr;
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case 0x4: return dma->channels[channel].bcr.raw;
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case 0x8: return dma->channels[channel].chcr.raw;
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default: Helpers::panic("[ FATAL ] Unhandled DMA read32 0x%08x\n", paddr);
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}
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}
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else if (paddr == 0x1f8010f0) return dma->dpcr;
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else if (paddr == 0x1f8010f4) return dma->dicr;
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// Timers
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else if (Helpers::inRangeSized<u32>(paddr, (u32)MemoryBase::Timer, (u32)MemorySize::Timer)) return 0;
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else if (paddr == 0x1f80101C) return 0x00070777; // Expansion 2 Delay/Size (usually 00070777h) (128 bytes, 8bit bus)
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else
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Helpers::dump("ramdump.bin", ram, 2_MB);
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Helpers::panic("[ FATAL ] Unhandled read32 0x%08x (virtual 0x%08x) @ pc 0x%08x\n", paddr, vaddr, core->pc);
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}
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template<>
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void Memory::write(u32 vaddr, u8 data) {
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const auto page = vaddr >> 16;
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const auto pointer = writeTable[page];
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// Use fast memory if the address is in the fastmem table
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if (pointer) {
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*(u8*)(pointer + (vaddr & 0xffff)) = data;
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return;
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}
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u32 paddr = maskAddress(vaddr);
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if (Helpers::inRangeSized<u32>(paddr, 0x1f800000, 1_KB)) scratchpad[paddr - 0x1f800000] = data;
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// CDROM
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else if (paddr == 0x1f801800) cdrom->writeStatus(data);
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else if (paddr == 0x1f801801) {
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switch (cdrom->getIndex()) {
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case 0: {
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cdrom->executeCommand(data);
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break;
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}
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default:
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Helpers::panic("[ FATAL ] Unhandled CDROM write8 0x1f801801.%d <- 0x%02x\n", cdrom->getIndex(), data);
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}
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}
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else if (paddr == 0x1f801802) {
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switch (cdrom->getIndex()) {
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case 0: {
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cdrom->pushParam(data);
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break;
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}
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case 1: {
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cdrom->writeIE(data);
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break;
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}
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default:
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Helpers::panic("[ FATAL ] Unhandled CDROM write8 0x1f801802.%d <- 0x%02x\n", cdrom->getIndex(), data);
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}
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}
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else if (paddr == 0x1f801803) {
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switch (cdrom->getIndex()) {
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case 1: {
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cdrom->writeIF(data);
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break;
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}
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default:
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Helpers::panic("[ FATAL ] Unhandled CDROM write8 0x1f801803.%d <- 0x%02x\n", cdrom->getIndex(), data);
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}
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}
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else if (paddr == 0x1f802041) return; // POST - External 7-segment Display (W)
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else
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Helpers::panic("[ FATAL ] Unhandled write8 0x%08x (virtual 0x%08x) <- 0x%02x\n", paddr, vaddr, data);
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}
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template<>
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void Memory::write(u32 vaddr, u16 data) {
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const auto page = vaddr >> 16;
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const auto pointer = writeTable[page];
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// Use fast memory if the address is in the fastmem table
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if (pointer) {
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*(u16*)(pointer + (vaddr & 0xffff)) = data;
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return;
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}
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u32 paddr = maskAddress(vaddr);
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if (Helpers::inRangeSized<u32>(paddr, 0x1f800000, 1_KB)) {
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std::memcpy(&scratchpad[paddr - 0x1f800000], &data, sizeof(u16));
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}
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// Interrupt
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else if (paddr == 0x1f801070) interrupt->writeIstat(data);
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else if (paddr == 0x1f801074) interrupt->writeImask(data);
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// SIO
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else if (Helpers::inRangeSized<u32>(paddr, (u32)MemoryBase::SIO, (u32)MemorySize::SIO)) return;
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// SPU
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else if (Helpers::inRangeSized<u32>(paddr, (u32)MemoryBase::SPU, (u32)MemorySize::SPU)) return;
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// Timers
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else if (Helpers::inRangeSized<u32>(paddr, (u32)MemoryBase::Timer, (u32)MemorySize::Timer)) return;
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else
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Helpers::panic("[ FATAL ] Unhandled write16 0x%08x (virtual 0x%08x) <- 0x%04x\n", paddr, vaddr, data);
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}
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template<>
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void Memory::write(u32 vaddr, u32 data) {
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const auto page = vaddr >> 16;
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const auto pointer = writeTable[page];
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// Use fast memory if the address is in the fastmem table
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if (pointer) {
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*(u32*)(pointer + (vaddr & 0xffff)) = data;
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return;
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}
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u32 paddr = maskAddress(vaddr);
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if (Helpers::inRangeSized<u32>(paddr, 0x1f800000, 1_KB)) {
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std::memcpy(&scratchpad[paddr - 0x1f800000], &data, sizeof(u32));
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}
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// GPU
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else if (paddr == 0x1f801810) gpu->writeGp0(data);
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else if (paddr == 0x1f801814) gpu->writeGp1(data);
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// Interrupt
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else if (paddr == 0x1f801070) interrupt->writeIstat(data);
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else if (paddr == 0x1f801074) interrupt->writeImask(data);
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// DMA
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else if (Helpers::inRange<u32>(paddr, 0x1f801080, 0x1f8010e8)) {
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const auto channel = ((paddr >> 4) & 0xf) - 8;
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Helpers::debugAssert(channel < 7, "Tried to access %dth DMA channel", channel); // Should not get triggered
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switch (paddr & 0xf) {
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case 0x0: dma->channels[channel].madr = data; break;
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case 0x4: dma->channels[channel].bcr.raw = data; break;
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case 0x8: {
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dma->channels[channel].chcr.raw = data;
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if (dma->channels[channel].shouldStartDMA()) {
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dma->doDMA(channel, this);
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}
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break;
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}
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default: Helpers::panic("[ FATAL ] Unhandled DMA write32 0x%08x <- 0x%08x\n", paddr, data);
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}
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}
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else if (paddr == 0x1f8010f0) dma->dpcr = data;
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else if (paddr == 0x1f8010f4) dma->dicr = data;
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// Timers
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else if (Helpers::inRangeSized<u32>(paddr, (u32)MemoryBase::Timer, (u32)MemorySize::Timer)) return;
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else if (paddr == 0x1f801000) return; // Expansion 1 Base Address (usually 1F000000h)
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else if (paddr == 0x1f801004) return; // Expansion 2 Base Address (usually 1F802000h)
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else if (paddr == 0x1f801008) return; // Expansion 1 Delay/Size (usually 0013243Fh) (512Kbytes, 8bit bus)
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else if (paddr == 0x1f80100C) return; // Expansion 3 Delay/Size (usually 00003022h) (1 byte)
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else if (paddr == 0x1f801010) return; // BIOS ROM Delay/Size (usually 0013243Fh) (512Kbytes, 8bit bus)
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else if (paddr == 0x1f801014) return; // SPU Delay/Size (200931E1h) (use 220931E1h for SPU-RAM reads)
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else if (paddr == 0x1f801018) return; // CDROM Delay/Size (00020843h or 00020943h)
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else if (paddr == 0x1f80101C) return; // Expansion 2 Delay/Size (usually 00070777h) (128 bytes, 8bit bus)
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else if (paddr == 0x1f801020) return; // COM_DELAY / COMMON_DELAY (00031125h or 0000132Ch or 00001325h)
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else if (paddr == 0x1f801060) return; // RAM_SIZE (R/W) (usually 00000B88h) (or 00000888h)
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else if (paddr == 0xfffe0130) return; // Cache Control (R/W)
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else
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Helpers::panic("[ FATAL ] Unhandled write32 0x%08x (virtual 0x%08x) <- 0x%08x\n", paddr, vaddr, data);
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} |