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@ -3,4 +3,5 @@
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A WIP PlayStation 2 emulator
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Currently implemented:
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Some Emotion Engine opcodes
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@ -30,4 +30,6 @@ Bus::Bus(std::string fileName, bool& s)
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s = true;
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printf("[emu/Bus]: %s: Bus initialized\n", __FUNCTION__);
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console.open("log.txt");
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}
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@ -2,6 +2,7 @@
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#include <bits/stdint-uintn.h>
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#include <string>
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#include <fstream>
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class Bus
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{
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@ -10,6 +11,8 @@ private:
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uint8_t bios[0x400000];
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uint8_t scratchpad[0x4000];
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std::ofstream console;
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uint32_t Translate(uint32_t addr)
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{
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if (addr <= 0x7FFFFFFF)
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@ -35,6 +38,14 @@ public:
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if (addr >= 0x1FC00000 && addr < 0x21C00000)
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return *(T*)&bios[addr - 0x1FC00000];
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if (addr >= 0x70000000 && addr < 0x70004000)
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return *(T*)&scratchpad[addr - 0x70000000];
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switch (addr)
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{
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case 0x1000f130: // SIO status
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return 0;
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}
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printf("[emu/Bus]: %s: Failed to read from address 0x%08x\n", __FUNCTION__, addr);
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exit(1);
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@ -53,10 +64,17 @@ public:
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switch (addr)
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{
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// misc SIO settings
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case 0x1000f100:
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case 0x1000f120:
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case 0x1000f140:
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case 0x1000f150:
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case 0x1000f500:
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return;
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case 0x1000f180:
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console << (char)data;
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console.flush();
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return;
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}
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printf("[emu/Bus]: %s: Write to unknown addr 0x%08x\n", __FUNCTION__, addr);
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@ -13,12 +13,20 @@ EmotionEngine::EmotionEngine(Bus* bus)
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next_pc = pc + 4;
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cop0_regs[15] = 0x2E20;
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for (int i = 0; i < 128; i++)
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{
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icache[i].tag[0] = 1 << 31;
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icache[i].tag[1] = 1 << 31;
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icache[i].lfu[0] = false;
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icache[i].lfu[1] = false;
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}
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}
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void EmotionEngine::Clock()
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{
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Opcode instr;
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instr.full = Read32Instr(pc);
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instr.full = Read32(pc, true);
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AdvancePC();
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@ -37,6 +45,9 @@ void EmotionEngine::Clock()
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case 0x00:
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sll(instr);
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break;
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case 0x03:
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sra(instr);
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break;
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case 0x08:
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jr(instr);
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break;
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@ -46,9 +57,15 @@ void EmotionEngine::Clock()
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case 0x0F:
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printf("sync\n");
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break;
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case 0x12:
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mflo(instr);
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break;
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case 0x18:
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mult(instr);
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break;
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case 0x1B:
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divu(instr);
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break;
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case 0x25:
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op_or(instr);
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break;
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@ -62,9 +79,26 @@ void EmotionEngine::Clock()
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}
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}
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break;
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case 0x03:
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case 0x01:
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{
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switch (instr.i_type.rt)
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{
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case 0x00:
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bltz(instr);
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break;
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default:
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printf("[emu/CPU]: %s: Unknown regimm instruction 0x%08x (0x%02x)\n", __FUNCTION__, instr.full, instr.i_type.rt);
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Application::Exit(1);
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break;
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}
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}
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break;
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case 0x02:
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j(instr);
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break;
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case 0x03:
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jal(instr);
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break;
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case 0x04:
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beq(instr);
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break;
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@ -77,6 +111,9 @@ void EmotionEngine::Clock()
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case 0x0A:
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slti(instr);
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break;
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case 0x0B:
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sltiu(instr);
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break;
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case 0x0C:
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andi(instr);
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break;
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@ -106,9 +143,33 @@ void EmotionEngine::Clock()
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}
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}
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break;
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case 0x14:
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beql(instr);
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break;
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case 0x15:
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bnel(instr);
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break;
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case 0x20:
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lb(instr);
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break;
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case 0x23:
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lw(instr);
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break;
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case 0x24:
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lbu(instr);
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break;
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case 0x28:
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sb(instr);
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break;
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case 0x2B:
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sw(instr);
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break;
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case 0x37:
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ld(instr);
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break;
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case 0x39:
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swc1(instr);
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break;
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case 0x3f:
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sd(instr);
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break;
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@ -124,4 +185,5 @@ void EmotionEngine::Dump()
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{
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for (int i = 0; i < 32; i++)
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printf("[emu/CPU]: %s: %s\t->\t%s\n", __FUNCTION__, Reg(i), print_128(regs[i]));
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printf("[emu/CPU]: %s: pc\t->\t0x%08x\n", __FUNCTION__, pc-4);
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}
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@ -15,6 +15,15 @@ private:
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uint32_t pc, next_pc;
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uint64_t hi, lo;
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struct COP1
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{
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union
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{
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float f[32] = {0.0f};
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uint32_t i[32];
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};
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} cop1;
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struct CacheTag
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{
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bool valid = false;
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@ -23,47 +32,68 @@ private:
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uint32_t page = 0;
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};
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struct Cache
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struct ICacheLine
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{
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CacheTag tag[2];
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uint8_t data[2][64] = {0};
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} icache[128], dcache[64];
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bool lfu[2];
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uint32_t tag[2];
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uint8_t data[2][64];
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};
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ICacheLine icache[128];
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bool isCacheEnabled = false;
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uint32_t Read32Instr(uint32_t addr)
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uint32_t Read32(uint32_t addr, bool isInstr = false)
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{
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if (!bus->IsCacheable(addr) || !isCacheEnabled)
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if (!bus->IsCacheable(addr) || !isCacheEnabled || !isInstr)
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return bus->read<uint32_t>(addr);
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uint32_t page = (addr >> 14);
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uint32_t index = (addr >> 5) & 8;
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uint32_t offset = addr & 0x3F;
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int index = (addr >> 6) & 0x7F;
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uint16_t tag = addr >> 13;
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int off = addr & 0x3F;
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Cache& line = icache[index];
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ICacheLine& line = icache[index];
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for (int way = 0; way < 2; way++)
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if (line.tag[0] != tag)
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{
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if (line.tag[way].page == page && line.tag[way].valid)
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if (line.tag[1] != tag)
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{
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return *((uint32_t*)&line.data[way][offset]);
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printf("Cache miss for addr 0x%08x\n", addr);
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if (line.tag[0] & (1 << 31))
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{
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line.lfu[0] ^= true;
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line.tag[0] = tag;
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for (int i = 0; i < 64; i++)
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line.data[0][i] = bus->read<uint8_t>((addr & 0xFFFFFFC0) + i);
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return *(uint32_t*)&line.data[0][off];
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}
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else if (line.tag[1] & (1 << 31))
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{
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line.lfu[1] ^= true;
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line.tag[1] = tag;
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for (int i = 0; i < 64; i++)
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line.data[1][i] = bus->read<uint8_t>((addr & 0xFFFFFFC0) + i);
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return *(uint32_t*)&line.data[1][off];
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}
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else
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{
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int replace = line.lfu[0] ^ line.lfu[1];
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line.lfu[replace] ^= true;
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line.lfu[replace] = tag;
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for (int i = 0; i < 64; i++)
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line.data[replace][i] = bus->read<uint8_t>((addr & 0xFFFFFFC0) + i);
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return *(uint32_t*)&line.data[replace][off];
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}
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}
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else
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{
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return *(uint32_t*)&line.data[1][off];
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}
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}
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// Welp, cache miss
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printf("[emu/CPU]: Cache miss for address 0x%08x\n", addr);
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int replace = 0;
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if (!line.tag[0].valid && line.tag[1].valid)
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replace = 0;
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else if (line.tag[0].valid && !line.tag[1].valid)
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replace = 1;
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else
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replace = line.tag[0].lrf ^ line.tag[1].lrf;
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for (int i = 0; i < 64; i++)
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line.data[replace][i] = bus->read<uint8_t>((page << 14) + i);
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return *(uint32_t*)&line.data[replace][offset];
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{
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return *(uint32_t*)&line.data[0][off];
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}
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}
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void Write32(uint32_t addr, uint32_t data)
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@ -74,43 +104,7 @@ private:
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return;
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}
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uint32_t page = (addr >> 13);
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uint32_t index = (addr >> 5) & 0b1111111;
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uint32_t offset = addr & 0x3F;
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Cache& line = dcache[index];
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for (int way = 0; way < 2; way++)
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{
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if (line.tag[way].page == page && line.tag[way].valid)
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{
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*((uint32_t*)&line.data[way][offset]) = data;
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line.tag[way].dirty = true; // We mark as dirty to flush back to main memory on eviction
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}
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}
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printf("[emu/CPU]: Cache miss for address 0x%08x\n", addr);
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int replace = 0;
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if (!line.tag[0].valid && line.tag[1].valid)
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replace = 0;
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else if (line.tag[0].valid && !line.tag[1].valid)
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replace = 1;
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else
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replace = line.tag[0].lrf ^ line.tag[1].lrf;
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if (line.tag[replace].dirty)
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{
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for (int i = 0; i < 64; i++)
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bus->write((page << 13) + i, line.data[replace][i]);
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}
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for (int i = 0; i < 64; i++)
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{
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line.data[replace][i] = bus->read<uint8_t>((page << 13) + i);
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}
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*(uint32_t*)&line.data[replace][offset] = data;
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line.tag[replace].dirty = true;
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}
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void Write64(uint32_t addr, uint64_t data)
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@ -120,66 +114,43 @@ private:
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bus->write(addr, data);
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return;
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}
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uint32_t page = (addr >> 13);
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uint32_t index = (addr >> 5) & 0b1111111;
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uint32_t offset = addr & 0x3F;
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Cache& line = dcache[index];
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for (int way = 0; way < 2; way++)
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{
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if (line.tag[way].page == page && line.tag[way].valid)
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{
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*((uint64_t*)&line.data[way][offset]) = data;
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line.tag[way].dirty = true; // We mark as dirty to flush back to main memory on eviction
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}
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}
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printf("[emu/CPU]: Cache miss for address 0x%08x\n", addr);
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int replace = 0;
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if (!line.tag[0].valid && line.tag[1].valid)
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replace = 0;
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else if (line.tag[0].valid && !line.tag[1].valid)
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replace = 1;
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else
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replace = line.tag[0].lrf ^ line.tag[1].lrf;
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if (line.tag[replace].dirty)
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{
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for (int i = 0; i < 64; i++)
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bus->write((page << 13) + i, line.data[replace][i]);
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}
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for (int i = 0; i < 64; i++)
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{
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line.data[replace][i] = bus->read<uint8_t>((page << 13) + i);
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}
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*(uint64_t*)&line.data[replace][offset] = data;
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line.tag[replace].dirty = true;
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}
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void j(Opcode i); // 0x03
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void j(Opcode i); // 0x02
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void jal(Opcode i); // 0x03
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void beq(Opcode i); // 0x04
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void bne(Opcode i); // 0x05
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void addiu(Opcode i); // 0x09
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void slti(Opcode i); // 0x0A
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void sltiu(Opcode i); // 0x0B
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void andi(Opcode i); // 0x0C
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void ori(Opcode i); // 0x0D
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void lui(Opcode i); // 0x0F
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void mfc0(Opcode i); // 0x10 0x00
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void mtc0(Opcode i); // 0x10 0x04
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void beql(Opcode i); // 0x14
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void bnel(Opcode i); // 0x15
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void lb(Opcode i); // 0x20
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void lw(Opcode i); // 0x23
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void lbu(Opcode i); // 0x24
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void sb(Opcode i); // 0x28
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void sw(Opcode i); // 0x2B
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void ld(Opcode i); // 0x37
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void swc1(Opcode i); // 0x39
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void sd(Opcode i); // 0x3f
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void sll(Opcode i); // 0x00
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void sra(Opcode i); // 0x03
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void jr(Opcode i); // 0x08
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void jalr(Opcode i); // 0x09
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void mflo(Opcode i); // 0x12
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void mult(Opcode i); // 0x18
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void divu(Opcode i); // 0x1B
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void op_or(Opcode i); // 0x25
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void daddu(Opcode i); // 0x2d
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void bltz(Opcode i); // 0x00
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void AdvancePC()
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{
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pc = next_pc;
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|
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@ -4,6 +4,7 @@
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#include <cstdio>
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#include <emu/cpu/EmotionEngine.h>
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void EmotionEngine::j(Opcode i)
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{
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uint32_t target = (i.j_type.target << 2);
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@ -11,6 +12,14 @@ void EmotionEngine::j(Opcode i)
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printf("j 0x%08x\n", next_pc);
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}
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void EmotionEngine::jal(Opcode i)
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{
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uint32_t target = (i.j_type.target << 2);
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regs[31].u64[0] = next_pc;
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next_pc = (pc & 0xF0000000) | target;
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printf("jal 0x%08x\n", next_pc);
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}
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void EmotionEngine::beq(Opcode i)
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{
|
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int32_t imm = (int32_t)((uint32_t)i.i_type.imm << 2);
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@ -41,38 +50,44 @@ void EmotionEngine::addiu(Opcode i)
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int rs = i.i_type.rs;
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int32_t imm = (int16_t)(uint32_t)i.i_type.imm;
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regs[rt].u32[0] = (uint32_t)((int32_t)regs[rt].u32[0] + imm);
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regs[rt].u64[0] = (uint32_t)((int32_t)regs[rt].u32[0] + imm);
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printf("addiu %s, %s, %d\n", Reg(rt), Reg(rs), imm);
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}
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void EmotionEngine::slti(Opcode i)
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{
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regs[i.i_type.rt].u32[0] = (int32_t)regs[i.i_type.rs].u32[0] < (int32_t)(uint32_t)i.i_type.imm;
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regs[i.i_type.rt].u64[0] = (int32_t)regs[i.i_type.rs].u32[0] < (int32_t)(uint32_t)i.i_type.imm;
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printf("slti %s, %s, 0x%04x\n", Reg(i.i_type.rt), Reg(i.i_type.rs), i.i_type.imm);
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}
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void EmotionEngine::sltiu(Opcode i)
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{
|
||||
regs[i.i_type.rt].u64[0] = regs[i.i_type.rs].u32[0] < (uint32_t)i.i_type.imm;
|
||||
printf("sltiu %s, %s, 0x%04x\n", Reg(i.i_type.rt), Reg(i.i_type.rs), i.i_type.imm);
|
||||
}
|
||||
|
||||
void EmotionEngine::andi(Opcode i)
|
||||
{
|
||||
regs[i.i_type.rt].u32[0] = regs[i.i_type.rs].u32[0] & (uint32_t)(int32_t)i.i_type.imm;
|
||||
regs[i.i_type.rt].u64[0] = regs[i.i_type.rs].u32[0] & (uint32_t)(int32_t)i.i_type.imm;
|
||||
printf("andi %s, %s, 0x%08x\n", Reg(i.i_type.rt), Reg(i.i_type.rs), i.i_type.imm);
|
||||
}
|
||||
|
||||
void EmotionEngine::ori(Opcode i)
|
||||
{
|
||||
regs[i.i_type.rt].u32[0] = regs[i.i_type.rs].u32[0] | (uint32_t)(int32_t)i.i_type.imm;
|
||||
regs[i.i_type.rt].u64[0] = regs[i.i_type.rs].u32[0] | (uint32_t)(int32_t)i.i_type.imm;
|
||||
printf("ori %s, %s, 0x%08x\n", Reg(i.i_type.rt), Reg(i.i_type.rs), i.i_type.imm);
|
||||
}
|
||||
|
||||
void EmotionEngine::lui(Opcode i)
|
||||
{
|
||||
regs[i.i_type.rt].u32[0] = (int32_t)((uint32_t)i.i_type.imm << 16);
|
||||
regs[i.i_type.rt].u64[0] = ((uint32_t)i.i_type.imm << 16);
|
||||
printf("lui %s, 0x%08x\n", Reg(i.i_type.rt), regs[i.i_type.rt].u32[0]);
|
||||
}
|
||||
|
||||
void EmotionEngine::mfc0(Opcode i)
|
||||
{
|
||||
regs[i.r_type.rt].u32[0] = cop0_regs[i.r_type.rd];
|
||||
regs[i.r_type.rt].u64[0] = cop0_regs[i.r_type.rd];
|
||||
printf("mfc0 %s, r%d\n", Reg(i.r_type.rt), i.r_type.rd);
|
||||
}
|
||||
|
||||
|
|
@ -82,6 +97,89 @@ void EmotionEngine::mtc0(Opcode i)
|
|||
printf("mtc0 %s, r%d\n", Reg(i.r_type.rt), i.r_type.rd);
|
||||
}
|
||||
|
||||
void EmotionEngine::beql(Opcode i)
|
||||
{
|
||||
int32_t imm = (int32_t)((uint32_t)i.i_type.imm << 2);
|
||||
|
||||
printf("beql %s, %s, 0x%08x\n", Reg(i.i_type.rs), Reg(i.i_type.rt), next_pc + imm);
|
||||
|
||||
if ((int32_t)regs[i.i_type.rs].u32[0] == (int32_t)regs[i.i_type.rt].u32[0])
|
||||
{
|
||||
next_pc = pc + imm;
|
||||
}
|
||||
else
|
||||
AdvancePC(); // Skip delay slot
|
||||
}
|
||||
|
||||
void EmotionEngine::bnel(Opcode i)
|
||||
{
|
||||
int32_t imm = (int32_t)((uint32_t)i.i_type.imm << 2);
|
||||
|
||||
bool taken = false;
|
||||
|
||||
if ((int32_t)regs[i.i_type.rs].u32[0] != (int32_t)regs[i.i_type.rt].u32[0])
|
||||
{
|
||||
next_pc = pc + imm;
|
||||
taken = true;
|
||||
}
|
||||
else
|
||||
AdvancePC(); // Skip delay slot
|
||||
|
||||
printf("bnel %s, %s, 0x%08x (%s)\n", Reg(i.i_type.rs), Reg(i.i_type.rt), pc + imm, taken ? "taken" : "");
|
||||
}
|
||||
|
||||
void EmotionEngine::lb(Opcode i)
|
||||
{
|
||||
int base = i.i_type.rs;
|
||||
int rt = i.i_type.rt;
|
||||
int16_t off = (int16_t)i.i_type.imm;
|
||||
|
||||
uint32_t addr = regs[base].u32[0] + off;
|
||||
|
||||
regs[rt].u64[0] = (int64_t)((uint8_t)(Read32(addr) & 0xFF));
|
||||
|
||||
printf("lb %s, %d(%s)\n", Reg(rt), off, Reg(base));
|
||||
}
|
||||
|
||||
void EmotionEngine::lw(Opcode i)
|
||||
{
|
||||
int base = i.i_type.rs;
|
||||
int rt = i.i_type.rt;
|
||||
int16_t off = (int16_t)i.i_type.imm;
|
||||
|
||||
uint32_t addr = regs[base].u32[0] + off;
|
||||
|
||||
regs[rt].u32[0] = bus->read<uint32_t>(addr);
|
||||
|
||||
printf("lw %s, %d(%s)\n", Reg(rt), off, Reg(base));
|
||||
}
|
||||
|
||||
void EmotionEngine::lbu(Opcode i)
|
||||
{
|
||||
int base = i.i_type.rs;
|
||||
int rt = i.i_type.rt;
|
||||
int16_t off = (int16_t)i.i_type.imm;
|
||||
|
||||
uint32_t addr = regs[base].u32[0] + off;
|
||||
|
||||
regs[rt].u64[0] = Read32(addr) & 0xFF;
|
||||
|
||||
printf("lbu %s, %d(%s)\n", Reg(rt), off, Reg(base));
|
||||
}
|
||||
|
||||
void EmotionEngine::sb(Opcode i)
|
||||
{
|
||||
int base = i.i_type.rs;
|
||||
int rt = i.i_type.rt;
|
||||
int16_t off = (int16_t)i.i_type.imm;
|
||||
|
||||
uint32_t addr = regs[base].u32[0] + off;
|
||||
|
||||
bus->write<uint8_t>(addr, regs[rt].u32[0] & 0xFF);
|
||||
|
||||
printf("sb %s, %d(%s)\n", Reg(rt), off, Reg(base));
|
||||
}
|
||||
|
||||
void EmotionEngine::sw(Opcode i)
|
||||
{
|
||||
int base = i.i_type.rs;
|
||||
|
|
@ -95,6 +193,32 @@ void EmotionEngine::sw(Opcode i)
|
|||
printf("sw %s, %d(%s)\n", Reg(rt), off, Reg(base));
|
||||
}
|
||||
|
||||
void EmotionEngine::ld(Opcode i)
|
||||
{
|
||||
int base = i.i_type.rs;
|
||||
int rt = i.i_type.rt;
|
||||
int16_t off = (int16_t)i.i_type.imm;
|
||||
|
||||
uint32_t addr = regs[base].u32[0] + off;
|
||||
|
||||
regs[rt].u64[0] = bus->read<uint64_t>(addr);
|
||||
|
||||
printf("ld %s, %d(%s)\n", Reg(rt), off, Reg(base));
|
||||
}
|
||||
|
||||
void EmotionEngine::swc1(Opcode i)
|
||||
{
|
||||
int base = i.i_type.rs;
|
||||
int rt = i.i_type.rt;
|
||||
int16_t off = (int16_t)i.i_type.imm;
|
||||
|
||||
uint32_t addr = regs[base].u32[0] + off;
|
||||
|
||||
Write32(addr, cop1.i[rt]);
|
||||
|
||||
printf("swc1 f%d, %d(%s)\n", rt, off, Reg(base));
|
||||
}
|
||||
|
||||
void EmotionEngine::sd(Opcode i)
|
||||
{
|
||||
int base = i.i_type.rs;
|
||||
|
|
@ -122,22 +246,43 @@ void EmotionEngine::sll(Opcode i)
|
|||
int rt = i.r_type.rt;
|
||||
int sa = i.r_type.sa;
|
||||
|
||||
regs[rd].u32[0] = regs[rt].u32[0] << sa;
|
||||
regs[rd].u64[0] = regs[rt].u32[0] << sa;
|
||||
|
||||
printf("sll %s, %s, %d\n", Reg(rd), Reg(rt), sa);
|
||||
}
|
||||
|
||||
void EmotionEngine::sra(Opcode i)
|
||||
{
|
||||
int rd = i.r_type.rd;
|
||||
int rt = i.r_type.rt;
|
||||
int sa = i.r_type.sa;
|
||||
|
||||
int32_t reg = (int32_t)regs[rt].u32[0];
|
||||
regs[rd].u64[0] = reg >> sa;
|
||||
|
||||
printf("sra %s, %s, %d\n", Reg(rd), Reg(rt), sa);
|
||||
}
|
||||
|
||||
void EmotionEngine::jalr(Opcode i)
|
||||
{
|
||||
int rs = i.r_type.rs;
|
||||
int rd = i.r_type.rd;
|
||||
|
||||
regs[rd].u32[0] = next_pc;
|
||||
regs[rd].u64[0] = next_pc;
|
||||
next_pc = regs[rs].u32[0];
|
||||
|
||||
printf("jalr %s, %s\n", Reg(rs), Reg(rd));
|
||||
}
|
||||
|
||||
void EmotionEngine::mflo(Opcode i)
|
||||
{
|
||||
int rd = i.r_type.rd;
|
||||
|
||||
regs[rd].u64[0] = lo;
|
||||
|
||||
printf("mflo %s\n", Reg(rd));
|
||||
}
|
||||
|
||||
void EmotionEngine::mult(Opcode i)
|
||||
{
|
||||
int rs = i.r_type.rs;
|
||||
|
|
@ -148,10 +293,29 @@ void EmotionEngine::mult(Opcode i)
|
|||
int64_t reg2 = (int64_t)regs[rt].u32[0];
|
||||
int64_t result = reg1 * reg2;
|
||||
|
||||
regs[rd].u32[0] = lo = (int32_t)(result & 0xFFFFFFFF);
|
||||
regs[rd].u64[0] = lo = (int32_t)(result & 0xFFFFFFFF);
|
||||
hi = (int32_t)(result >> 32);
|
||||
|
||||
printf("mult %s, %s, %s\n", Reg(rd), Reg(rs), Reg(rt));
|
||||
printf("mult %s, %s, %s (0x%08x, 0x%08x)\n", Reg(rd), Reg(rs), Reg(rt), hi, lo);
|
||||
}
|
||||
|
||||
void EmotionEngine::divu(Opcode i)
|
||||
{
|
||||
int rs = i.r_type.rs;
|
||||
int rt = i.r_type.rt;
|
||||
|
||||
if (regs[rt].u32[0] == 0)
|
||||
{
|
||||
hi = (int32_t)regs[rs].u32[0];
|
||||
lo = (int32_t)0xffffffff;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi = (int32_t)(regs[rs].u32[0] % regs[rt].u32[0]);
|
||||
lo = (int32_t)(regs[rs].u32[0] / regs[rt].u32[0]);
|
||||
}
|
||||
|
||||
printf("divu %s (0x%08x), %s (0x%08x) (0x%08x, 0x%08x)\n", Reg(rs), regs[rs].u32[0], Reg(rt), regs[rt].u32[0], hi, lo);
|
||||
}
|
||||
|
||||
void EmotionEngine::op_or(Opcode i)
|
||||
|
|
@ -160,7 +324,7 @@ void EmotionEngine::op_or(Opcode i)
|
|||
int rs = i.r_type.rs;
|
||||
int rt = i.r_type.rt;
|
||||
|
||||
regs[rd].u32[0] = regs[rt].u32[0] | regs[rs].u32[0];
|
||||
regs[rd].u64[0] = regs[rt].u32[0] | regs[rs].u32[0];
|
||||
|
||||
printf("or %s, %s, %s\n", Reg(rd), Reg(rt), Reg(rs));
|
||||
}
|
||||
|
|
@ -177,4 +341,19 @@ void EmotionEngine::daddu(Opcode i)
|
|||
regs[rd].u64[0] = reg1 + reg2;
|
||||
|
||||
printf("daddu %s, %s, %s\n", Reg(rd), Reg(rs), Reg(rt));
|
||||
}
|
||||
|
||||
void EmotionEngine::bltz(Opcode i)
|
||||
{
|
||||
int rs = i.i_type.rs;
|
||||
|
||||
int32_t val = (int32_t)regs[rs].u32[0];
|
||||
int32_t off = (int32_t)(i.i_type.imm << 2);
|
||||
|
||||
printf("bltz %s, 0x%08x\n", Reg(rs), pc + off);
|
||||
|
||||
if (val < 0)
|
||||
{
|
||||
next_pc = pc + off;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue