mirror of
https://github.com/mkwong98/HDNes.git
synced 2024-05-20 13:07:54 -04:00
298 lines
7.4 KiB
C++
298 lines
7.4 KiB
C++
#include "StdAfx.h"
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#include "mapper1.h"
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#include "sysState.h"
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mapper1::mapper1(void)
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{
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if(romDat->mirrorV){
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reg[0] = 0x02;
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}
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else{
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reg[0] = 0x03;
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}
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setMirroring();
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writeNum = 0;
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writeRegBuffer = 0;
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chr8KMode = false;
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prg32KMode = false;
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slotCSwap = false;
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chrReg0 = 0;
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chrReg1 = 0;
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prgReg = 0;
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wramDisable = false;
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setBankSwitching();
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}
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mapper1::~mapper1(void)
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{
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}
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void mapper1::setMirroring(){
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switch(reg[0] & 0x03){
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case 0x00:
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memDat->nameTableMirroring[0][0] = 0;
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memDat->nameTableMirroring[0][1] = 0;
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memDat->nameTableMirroring[1][0] = 0;
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memDat->nameTableMirroring[1][1] = 0;
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break;
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case 0x01:
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memDat->nameTableMirroring[0][0] = 1;
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memDat->nameTableMirroring[0][1] = 1;
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memDat->nameTableMirroring[1][0] = 1;
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memDat->nameTableMirroring[1][1] = 1;
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break;
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case 0x02:
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memDat->nameTableMirroring[0][0] = 0;
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memDat->nameTableMirroring[0][1] = 0;
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memDat->nameTableMirroring[1][0] = 1;
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memDat->nameTableMirroring[1][1] = 1;
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break;
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case 0x03:
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memDat->nameTableMirroring[0][0] = 0;
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memDat->nameTableMirroring[0][1] = 1;
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memDat->nameTableMirroring[1][0] = 0;
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memDat->nameTableMirroring[1][1] = 1;
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break;
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}
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}
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void mapper1::setBankSwitching(){
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Uint8 tmpReg;
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if(romDat->chrPageCount > 0){
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if(chr8KMode){
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tmpReg = chrReg0 & 0xFE;
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chrPtr[0] = &(romDat->chrROM[tmpReg << 12]);
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chrPtr[1] = &(romDat->chrROM[(tmpReg + 1) << 12]);
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}
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else{
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chrPtr[0] = &(romDat->chrROM[chrReg0 << 12]);
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chrPtr[1] = &(romDat->chrROM[chrReg1 << 12]);
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}
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}
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else{
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chrPtr[0] = &(romDat->chrRAM[0]);
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chrPtr[1] = &(romDat->chrRAM[0x1000]);
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}
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if(prg32KMode){
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prgPtr[0] = &(romDat->prgROM[(prgReg & 0xFE) << 14]);
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prgPtr[1] = &(romDat->prgROM[((prgReg & 0xFE) + 1) << 14]);
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}
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else{
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if(slotCSwap){
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prgPtr[0] = &(romDat->prgROM[0]);
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prgPtr[1] = &(romDat->prgROM[prgReg << 14]);
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}
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else{
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prgPtr[0] = &(romDat->prgROM[prgReg << 14]);
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if(romDat->prgPageCount <= 15){
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prgPtr[1] = &(romDat->prgROM[(romDat->prgPageCount - 1) << 14]);
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}
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else{
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prgPtr[1] = &(romDat->prgROM[0x3C000]);
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}
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}
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}
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}
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void mapper1::writeCPUData(Uint16 address, Uint8 data){
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Uint8 regID;
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if(address >= 0x6000){
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if(address < 0x8000){
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if(!wramDisable){
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romDat->batDat[address & 0x1FFF] = data;
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if(romDat->useBat)romDat->batChanged = true;
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}
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}
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else{
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if(data & 0x80){
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writeNum = 0;
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writeRegBuffer = 0;
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reg[0] = reg[0] | 0x0c;
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writeReg0(reg[0]);
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setBankSwitching();
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}
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else{
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if(writeNum < 5){
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writeRegBuffer = writeRegBuffer | ((data & 0x01) << writeNum);
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++writeNum;
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if(writeNum == 5){
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regID = (address >> 13) & 0x03;
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reg[regID] = writeRegBuffer;
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switch(regID){
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case 0:
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writeReg0(writeRegBuffer);
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break;
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case 1:
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writeReg1(writeRegBuffer);
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break;
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case 2:
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writeReg2(writeRegBuffer);
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break;
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case 3:
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writeReg3(writeRegBuffer);
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break;
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}
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setBankSwitching();
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writeNum = 0;
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writeRegBuffer = 0;
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}
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}
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}
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}
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}
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}
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void mapper1::writeReg0(Uint8 data){
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setMirroring();
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chr8KMode = ((data & 0x10) == 0);
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prg32KMode = ((data & 0x08) == 0);
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slotCSwap = ((data & 0x04) == 0);
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}
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void mapper1::writeReg1(Uint8 data){
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chrReg0 = data & 0x1F;
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}
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void mapper1::writeReg2(Uint8 data){
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chrReg1 = data & 0x1F;
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}
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void mapper1::writeReg3(Uint8 data){
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wramDisable = ((data & 0x10) != 0);
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prgReg = data & 0x0F;
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}
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Uint8 mapper1::readCPUData(Uint16 address, bool opRead){
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Uint8 bank;
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if(address >= 0x6000){
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if(address < 0x8000){
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if(!wramDisable) return romDat->batDat[address & 0x1FFF];
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}
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else{
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bank = ((address & 0x7FFF) >> 14);
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if(opRead) lastPrgRead = &(prgPtr[bank][address & 0x3FFF]) - romDat->prgROM;
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return prgPtr[bank][address & 0x3FFF];
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}
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}
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return 0;
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}
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void mapper1::writePPUData(Uint16 address, Uint8 data){
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if(address < 0x2000){
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if(romDat->chrPageCount == 0){
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romDat->chrRAM[address] = data;
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if(lastPrgRead != BAD_ADDRESS)
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romDat->chrRAMAddress[address >> 4] = lastPrgRead >> 4;
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}
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}
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}
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Uint8 mapper1::readPPUData(Uint16 address){
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Uint8 bank;
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if(address < 0x2000){
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bank = (address >> 12);
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if(romDat->chrPageCount > 0){
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return chrPtr[bank][address & 0x0FFF];
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}
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else{
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return romDat->chrRAM[address];
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}
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}
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return 0;
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}
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void mapper1::getPattern(Uint16 address, Uint8 row, bool isFirst, Uint8& data, Uint32& patternAddress, Uint32& ramAddress){
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Uint16 tmpAddress;
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Uint32 realAddress;
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Uint8 bank;
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tmpAddress = address;
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if(row >= 8){
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tmpAddress += 16;
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row -= 8;
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}
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if(!isFirst) tmpAddress += 8;
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if(romDat->chrPageCount > 0){
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bank = (tmpAddress >> 12);
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data = chrPtr[bank][(tmpAddress + row) & 0x0FFF];
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realAddress = &(chrPtr[bank][(tmpAddress + row) & 0x0FFF]) - romDat->chrROM;
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patternAddress = realAddress >> 4;
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}
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else{
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data = romDat->chrRAM[tmpAddress + row];
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ramAddress = tmpAddress & 0xFFF0;
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//patternAddress = BAD_ADDRESS;
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if(vid->chrRamMatch){
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patternAddress = romDat->chrRAMAddress[tmpAddress >> 4];
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}
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else{
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patternAddress = tmpAddress >> 4;
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}
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}
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}
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void mapper1::saveState(fstream* statefile){
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Uint32 offset;
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statefile->write((char *)(&writeRegBuffer), sizeof(Uint8));
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statefile->write((char *)(&writeNum), sizeof(Uint8));
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statefile->write((char *)(reg), sizeof(Uint8) * 4);
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statefile->write((char *)(&chr8KMode), sizeof(boolean));
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statefile->write((char *)(&prg32KMode), sizeof(boolean));
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statefile->write((char *)(&slotCSwap), sizeof(boolean));
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statefile->write((char *)(&chrReg0), sizeof(Uint8));
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statefile->write((char *)(&chrReg1), sizeof(Uint8));
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statefile->write((char *)(&wramDisable), sizeof(boolean));
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statefile->write((char *)(&prgReg), sizeof(Uint8));
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statefile->write((char *)(&lastPrgRead), sizeof(Uint32));
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offset = chrPtr[0] - romDat->chrROM;
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statefile->write((char *)(&offset), sizeof(Uint32));
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offset = chrPtr[1] - romDat->chrROM;
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statefile->write((char *)(&offset), sizeof(Uint32));
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offset = prgPtr[0] - romDat->prgROM;
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statefile->write((char *)(&offset), sizeof(Uint32));
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offset = prgPtr[1] - romDat->prgROM;
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statefile->write((char *)(&offset), sizeof(Uint32));
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}
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void mapper1::loadState(fstream* statefile){
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Uint32 offset;
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statefile->read((char *)(&writeRegBuffer), sizeof(Uint8));
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statefile->read((char *)(&writeNum), sizeof(Uint8));
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statefile->read((char *)(reg), sizeof(Uint8) * 4);
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statefile->read((char *)(&chr8KMode), sizeof(boolean));
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statefile->read((char *)(&prg32KMode), sizeof(boolean));
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statefile->read((char *)(&slotCSwap), sizeof(boolean));
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statefile->read((char *)(&chrReg0), sizeof(Uint8));
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statefile->read((char *)(&chrReg1), sizeof(Uint8));
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statefile->read((char *)(&wramDisable), sizeof(boolean));
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statefile->read((char *)(&prgReg), sizeof(Uint8));
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statefile->read((char *)(&lastPrgRead), sizeof(Uint32));
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statefile->read((char *)(&offset), sizeof(Uint32));
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chrPtr[0] = &(romDat->chrROM[offset]);
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statefile->read((char *)(&offset), sizeof(Uint32));
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chrPtr[1] = &(romDat->chrROM[offset]);
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statefile->read((char *)(&offset), sizeof(Uint32));
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prgPtr[0] = &(romDat->prgROM[offset]);
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statefile->read((char *)(&offset), sizeof(Uint32));
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prgPtr[1] = &(romDat->prgROM[offset]);
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setMirroring();
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setBankSwitching();
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}
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void mapper1::runCatchUp(unsigned int cycle){
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}
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void mapper1::resetCycleCount(){
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}
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