mirror of
https://github.com/Tinob/Ishiiruka.git
synced 2024-05-23 14:47:38 -04:00
496 lines
10 KiB
C++
496 lines
10 KiB
C++
// Copyright 2014 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "Common/Arm64Emitter.h"
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#include "Common/Common.h"
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#include "Common/StringUtil.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/PowerPC/PowerPC.h"
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#include "Core/PowerPC/PPCTables.h"
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#include "Core/PowerPC/JitArm64/Jit.h"
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#include "Core/PowerPC/JitArm64/JitArm64_RegCache.h"
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#include "Core/PowerPC/JitArm64/JitAsm.h"
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using namespace Arm64Gen;
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void JitArm64::ps_abs(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == b);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.FABS(64, VD, VB);
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}
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void JitArm64::ps_add(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.FADD(64, VD, VA, VB);
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}
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void JitArm64::ps_div(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.FDIV(64, VD, VA, VB);
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}
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void JitArm64::ps_madd(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.FMUL(64, V0, VA, VC);
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m_float_emit.FADD(64, VD, V0, VB);
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fpr.Unlock(V0);
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}
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void JitArm64::ps_madds0(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.DUP(64, V0, VC, 0);
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m_float_emit.FMUL(64, V0, V0, VA);
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m_float_emit.FADD(64, VD, V0, VB);
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fpr.Unlock(V0);
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}
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void JitArm64::ps_madds1(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.DUP(64, V0, VC, 1);
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m_float_emit.FMUL(64, V0, V0, VA);
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m_float_emit.FADD(64, VD, V0, VB);
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fpr.Unlock(V0);
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}
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void JitArm64::ps_merge00(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.TRN1(64, VD, VA, VB);
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}
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void JitArm64::ps_merge01(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.INS(64, VD, 0, VA, 0);
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m_float_emit.INS(64, VD, 1, VB, 1);
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}
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void JitArm64::ps_merge10(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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if (d != a && d != b)
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{
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m_float_emit.INS(64, VD, 0, VA, 1);
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m_float_emit.INS(64, VD, 1, VB, 0);
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}
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else
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{
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.INS(64, V0, 0, VA, 1);
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m_float_emit.INS(64, V0, 1, VB, 0);
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m_float_emit.ORR(VD, V0, V0);
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fpr.Unlock(V0);
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}
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}
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void JitArm64::ps_merge11(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.TRN2(64, VD, VA, VB);
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}
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void JitArm64::ps_mr(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 b = inst.FB, d = inst.FD;
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if (d == b)
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return;
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fpr.BindToRegister(d, false);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.ORR(VD, VB, VB);
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}
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void JitArm64::ps_mul(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.FMUL(64, VD, VA, VC);
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}
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void JitArm64::ps_muls0(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.DUP(64, V0, VC, 0);
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m_float_emit.FMUL(64, VD, VA, V0);
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fpr.Unlock(V0);
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}
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void JitArm64::ps_muls1(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.DUP(64, V0, VC, 1);
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m_float_emit.FMUL(64, VD, VA, V0);
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fpr.Unlock(V0);
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}
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void JitArm64::ps_msub(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.FMUL(64, V0, VA, VC);
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m_float_emit.FSUB(64, VD, V0, VB);
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fpr.Unlock(V0);
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}
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void JitArm64::ps_nabs(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == b);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.FABS(64, VD, VB);
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m_float_emit.FNEG(64, VD, VD);
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}
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void JitArm64::ps_neg(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == b);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.FNEG(64, VD, VB);
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}
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void JitArm64::ps_nmadd(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.FMUL(64, V0, VA, VC);
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m_float_emit.FADD(64, VD, V0, VB);
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m_float_emit.FNEG(64, VD, VD);
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fpr.Unlock(V0);
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}
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void JitArm64::ps_nmsub(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.FMUL(64, V0, VA, VC);
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m_float_emit.FSUB(64, VD, V0, VB);
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m_float_emit.FNEG(64, VD, VD);
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fpr.Unlock(V0);
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}
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void JitArm64::ps_res(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == b);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.FRSQRTE(64, VD, VB);
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}
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void JitArm64::ps_sel(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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if (d != a && d != b && d != c)
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{
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m_float_emit.FCMGE(64, VD, VA);
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m_float_emit.BSL(VD, VC, VB);
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}
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else
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{
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.FCMGE(64, V0, VA);
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m_float_emit.BSL(V0, VC, VB);
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m_float_emit.ORR(VD, V0, V0);
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fpr.Unlock(V0);
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}
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}
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void JitArm64::ps_sub(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VD = fpr.R(d);
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m_float_emit.FSUB(64, VD, VA, VB);
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}
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void JitArm64::ps_sum0(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.DUP(64, V0, VB, 1);
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if (d != c)
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{
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m_float_emit.FADD(64, VD, V0, VA);
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m_float_emit.INS(64, VD, 1, VC, 1);
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}
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else
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{
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m_float_emit.FADD(64, V0, V0, VA);
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m_float_emit.INS(64, VD, 0, V0, 0);
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}
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fpr.Unlock(V0);
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}
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void JitArm64::ps_sum1(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
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fpr.BindToRegister(d, d == a || d == b || d == c);
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ARM64Reg VA = fpr.R(a);
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ARM64Reg VB = fpr.R(b);
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ARM64Reg VC = fpr.R(c);
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ARM64Reg VD = fpr.R(d);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.DUP(64, V0, VA, 0);
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if (d != c)
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{
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m_float_emit.FADD(64, VD, V0, VB);
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m_float_emit.INS(64, VD, 0, VC, 0);
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}
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else
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{
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m_float_emit.FADD(64, V0, V0, VB);
|
|
m_float_emit.INS(64, VD, 1, V0, 1);
|
|
}
|
|
|
|
fpr.Unlock(V0);
|
|
}
|