diff --git a/Core/Gsu.Instructions.cpp b/Core/Gsu.Instructions.cpp
index ccf933e..d7fde8f 100644
--- a/Core/Gsu.Instructions.cpp
+++ b/Core/Gsu.Instructions.cpp
@@ -45,12 +45,12 @@ void Gsu::BRA()
 
 void Gsu::BLT()
 {
-	Branch(_state.SFR.Sign == _state.SFR.Overflow);
+	Branch((_state.SFR.Sign ^ _state.SFR.Overflow) == 1);
 }
 
 void Gsu::BGE()
 {
-	Branch(_state.SFR.Sign != _state.SFR.Overflow);
+	Branch((_state.SFR.Sign ^ _state.SFR.Overflow) == 0);
 }
 
 void Gsu::BNE()
diff --git a/Core/Gsu.cpp b/Core/Gsu.cpp
index e3aca33..bbc31e0 100644
--- a/Core/Gsu.cpp
+++ b/Core/Gsu.cpp
@@ -106,8 +106,8 @@ void Gsu::Exec()
 		case 0x03: LSR(); break;
 		case 0x04: ROL(); break;
 		case 0x05: BRA(); break;
-		case 0x06: BLT(); break;
-		case 0x07: BGE(); break;
+		case 0x06: BGE(); break;
+		case 0x07: BLT(); break;
 		case 0x08: BNE(); break;
 		case 0x09: BEQ(); break;
 		case 0x0A: BPL(); break;
diff --git a/Core/GsuDisUtils.cpp b/Core/GsuDisUtils.cpp
index b5473ee..f4c1624 100644
--- a/Core/GsuDisUtils.cpp
+++ b/Core/GsuDisUtils.cpp
@@ -38,8 +38,8 @@ void GsuDisUtils::GetDisassembly(DisassemblyInfo &info, string &out, uint32_t me
 		case 0x04: str.Write("ROL"); break;
 		
 		case 0x05: str.WriteAll("BRA "); getJumpTarget(); break;
-		case 0x06: str.WriteAll("BLT "); getJumpTarget(); break;
-		case 0x07: str.WriteAll("BGE "); getJumpTarget(); break;
+		case 0x06: str.WriteAll("BGE "); getJumpTarget(); break;
+		case 0x07: str.WriteAll("BLT "); getJumpTarget(); break;
 		case 0x08: str.WriteAll("BNE "); getJumpTarget(); break;
 		case 0x09: str.WriteAll("BEQ "); getJumpTarget(); break;
 		case 0x0A: str.WriteAll("BPL "); getJumpTarget(); break;