mirror of
https://github.com/NovaSquirrel/Mesen-X.git
synced 2024-06-01 02:48:18 -04:00
813aabb04a
Previously the CPU::StreamState function passed the extraScanlinesBeforeNmi value twice to Stream(). Change the second argument to extraScanlinesAfterNmi instead.
488 lines
18 KiB
C++
488 lines
18 KiB
C++
#include "stdafx.h"
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#include <random>
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#include <assert.h>
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#include "CPU.h"
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#include "PPU.h"
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#include "APU.h"
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#include "DeltaModulationChannel.h"
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#include "Debugger.h"
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#include "NsfMapper.h"
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#include "Console.h"
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CPU::CPU(shared_ptr<Console> console)
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{
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_console = console;
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_memoryManager = _console->GetMemoryManager();
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Func opTable[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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&CPU::BRK, &CPU::ORA, &CPU::HLT, &CPU::SLO, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, &CPU::SLO, &CPU::PHP, &CPU::ORA, &CPU::ASL_Acc, &CPU::AAC, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, &CPU::SLO, //0
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&CPU::BPL, &CPU::ORA, &CPU::HLT, &CPU::SLO, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, &CPU::SLO, &CPU::CLC, &CPU::ORA, &CPU::NOP, &CPU::SLO, &CPU::NOP, &CPU::ORA, &CPU::ASL_Memory, &CPU::SLO, //1
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&CPU::JSR, &CPU::AND, &CPU::HLT, &CPU::RLA, &CPU::BIT, &CPU::AND, &CPU::ROL_Memory, &CPU::RLA, &CPU::PLP, &CPU::AND, &CPU::ROL_Acc, &CPU::AAC, &CPU::BIT, &CPU::AND, &CPU::ROL_Memory, &CPU::RLA, //2
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&CPU::BMI, &CPU::AND, &CPU::HLT, &CPU::RLA, &CPU::NOP, &CPU::AND, &CPU::ROL_Memory, &CPU::RLA, &CPU::SEC, &CPU::AND, &CPU::NOP, &CPU::RLA, &CPU::NOP, &CPU::AND, &CPU::ROL_Memory, &CPU::RLA, //3
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&CPU::RTI, &CPU::EOR, &CPU::HLT, &CPU::SRE, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, &CPU::SRE, &CPU::PHA, &CPU::EOR, &CPU::LSR_Acc, &CPU::ASR, &CPU::JMP_Abs, &CPU::EOR, &CPU::LSR_Memory, &CPU::SRE, //4
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&CPU::BVC, &CPU::EOR, &CPU::HLT, &CPU::SRE, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, &CPU::SRE, &CPU::CLI, &CPU::EOR, &CPU::NOP, &CPU::SRE, &CPU::NOP, &CPU::EOR, &CPU::LSR_Memory, &CPU::SRE, //5
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&CPU::RTS, &CPU::ADC, &CPU::HLT, &CPU::RRA, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, &CPU::RRA, &CPU::PLA, &CPU::ADC, &CPU::ROR_Acc, &CPU::ARR, &CPU::JMP_Ind, &CPU::ADC, &CPU::ROR_Memory, &CPU::RRA, //6
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&CPU::BVS, &CPU::ADC, &CPU::HLT, &CPU::RRA, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, &CPU::RRA, &CPU::SEI, &CPU::ADC, &CPU::NOP, &CPU::RRA, &CPU::NOP, &CPU::ADC, &CPU::ROR_Memory, &CPU::RRA, //7
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&CPU::NOP, &CPU::STA, &CPU::NOP, &CPU::SAX, &CPU::STY, &CPU::STA, &CPU::STX, &CPU::SAX, &CPU::DEY, &CPU::NOP, &CPU::TXA, &CPU::UNK, &CPU::STY, &CPU::STA, &CPU::STX, &CPU::SAX, //8
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&CPU::BCC, &CPU::STA, &CPU::HLT, &CPU::AXA, &CPU::STY, &CPU::STA, &CPU::STX, &CPU::SAX, &CPU::TYA, &CPU::STA, &CPU::TXS, &CPU::TAS, &CPU::SYA, &CPU::STA, &CPU::SXA, &CPU::AXA, //9
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&CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, &CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, &CPU::TAY, &CPU::LDA, &CPU::TAX, &CPU::ATX, &CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, //A
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&CPU::BCS, &CPU::LDA, &CPU::HLT, &CPU::LAX, &CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, &CPU::CLV, &CPU::LDA, &CPU::TSX, &CPU::LAS, &CPU::LDY, &CPU::LDA, &CPU::LDX, &CPU::LAX, //B
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&CPU::CPY, &CPU::CPA, &CPU::NOP, &CPU::DCP, &CPU::CPY, &CPU::CPA, &CPU::DEC, &CPU::DCP, &CPU::INY, &CPU::CPA, &CPU::DEX, &CPU::AXS, &CPU::CPY, &CPU::CPA, &CPU::DEC, &CPU::DCP, //C
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&CPU::BNE, &CPU::CPA, &CPU::HLT, &CPU::DCP, &CPU::NOP, &CPU::CPA, &CPU::DEC, &CPU::DCP, &CPU::CLD, &CPU::CPA, &CPU::NOP, &CPU::DCP, &CPU::NOP, &CPU::CPA, &CPU::DEC, &CPU::DCP, //D
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&CPU::CPX, &CPU::SBC, &CPU::NOP, &CPU::ISB, &CPU::CPX, &CPU::SBC, &CPU::INC, &CPU::ISB, &CPU::INX, &CPU::SBC, &CPU::NOP, &CPU::SBC, &CPU::CPX, &CPU::SBC, &CPU::INC, &CPU::ISB, //E
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&CPU::BEQ, &CPU::SBC, &CPU::HLT, &CPU::ISB, &CPU::NOP, &CPU::SBC, &CPU::INC, &CPU::ISB, &CPU::SED, &CPU::SBC, &CPU::NOP, &CPU::ISB, &CPU::NOP, &CPU::SBC, &CPU::INC, &CPU::ISB //F
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};
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typedef AddrMode M;
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AddrMode addrMode[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //0
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//1
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M::Abs, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //2
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//3
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //4
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//5
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M::Imp, M::IndX, M::None, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imm, M::Ind, M::Abs, M::Abs, M::Abs, //6
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//7
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //8
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M::Rel, M::IndYW, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroY, M::ZeroY, M::Imp, M::AbsYW,M::Imp, M::AbsYW,M::AbsXW,M::AbsXW,M::AbsYW,M::AbsYW,//9
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //A
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M::Rel, M::IndY, M::None, M::IndY, M::ZeroX, M::ZeroX, M::ZeroY, M::ZeroY, M::Imp, M::AbsY, M::Imp, M::AbsY, M::AbsX, M::AbsX, M::AbsY, M::AbsY, //B
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //C
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//D
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M::Imm, M::IndX, M::Imm, M::IndX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imm, M::Abs, M::Abs, M::Abs, M::Abs, //E
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M::Rel, M::IndY, M::None, M::IndYW, M::ZeroX, M::ZeroX, M::ZeroX, M::ZeroX, M::Imp, M::AbsY, M::Imp, M::AbsYW,M::AbsX, M::AbsX, M::AbsXW,M::AbsXW,//F
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};
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memcpy(_opTable, opTable, sizeof(opTable));
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memcpy(_addrMode, addrMode, sizeof(addrMode));
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_instAddrMode = AddrMode::None;
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_state = {};
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_cycleCount = 0;
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_operand = 0;
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_spriteDmaTransfer = false;
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_spriteDmaOffset = 0;
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_needHalt = false;
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_ppuOffset = 0;
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_startClockCount = 6;
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_endClockCount = 6;
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_masterClock = 0;
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_dmcDmaRunning = false;
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_cpuWrite = false;
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_irqMask = 0;
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_state = {};
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_prevRunIrq = false;
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_runIrq = false;
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}
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void CPU::Reset(bool softReset, NesModel model)
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{
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_state.NMIFlag = false;
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_state.IRQFlag = 0;
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_spriteDmaTransfer = false;
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_spriteDmaOffset = 0;
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_needHalt = false;
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_dmcDmaRunning = false;
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_lastCrashWarning = 0;
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//Used by NSF code to disable Frame Counter & DMC interrupts
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_irqMask = 0xFF;
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//Use _memoryManager->Read() directly to prevent clocking the PPU/APU when setting PC at reset
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_state.PC = _memoryManager->Read(CPU::ResetVector) | _memoryManager->Read(CPU::ResetVector+1) << 8;
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_state.DebugPC = _state.PC;
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_state.PreviousDebugPC = _state.PC;
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if(softReset) {
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SetFlags(PSFlags::Interrupt);
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_state.SP -= 0x03;
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} else {
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_state.A = 0;
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_state.SP = 0xFD;
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_state.X = 0;
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_state.Y = 0;
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_state.PS = PSFlags::Interrupt;
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_runIrq = false;
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}
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uint8_t ppuDivider;
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uint8_t cpuDivider;
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switch(model) {
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default:
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case NesModel::NTSC:
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ppuDivider = 4;
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cpuDivider = 12;
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break;
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case NesModel::PAL:
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ppuDivider = 5;
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cpuDivider = 16;
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break;
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case NesModel::Dendy:
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ppuDivider = 5;
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cpuDivider = 15;
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break;
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}
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_cycleCount = -1;
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_masterClock = 0;
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uint8_t cpuOffset = 0;
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if(_console->GetSettings()->CheckFlag(EmulationFlags::RandomizeCpuPpuAlignment)) {
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std::random_device rd;
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std::mt19937 mt(rd());
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std::uniform_int_distribution<> distPpu(0, ppuDivider - 1);
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std::uniform_int_distribution<> distCpu(0, cpuDivider - 1);
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_ppuOffset = distPpu(mt);
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cpuOffset += distCpu(mt);
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string ppuAlignment = " PPU: " + std::to_string(_ppuOffset) + "/" + std::to_string(ppuDivider - 1);
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string cpuAlignment = " CPU: " + std::to_string(cpuOffset) + "/" + std::to_string(cpuDivider - 1);
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MessageManager::Log("CPU/PPU alignment -" + ppuAlignment + cpuAlignment);
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} else {
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_ppuOffset = 1;
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cpuOffset = 0;
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}
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_masterClock += cpuDivider + cpuOffset;
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//The CPU takes 8 cycles before it starts executing the ROM's code after a reset/power up
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for(int i = 0; i < 8; i++) {
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StartCpuCycle(true);
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EndCpuCycle(true);
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}
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}
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void CPU::Exec()
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{
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uint8_t opCode = GetOPCode();
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_instAddrMode = _addrMode[opCode];
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_operand = FetchOperand();
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(this->*_opTable[opCode])();
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if(_prevRunIrq || _prevNeedNmi) {
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IRQ();
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}
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}
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void CPU::IRQ()
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{
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#ifndef DUMMYCPU
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uint16_t originalPc = PC();
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#endif
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DummyRead(); //fetch opcode (and discard it - $00 (BRK) is forced into the opcode register instead)
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DummyRead(); //read next instruction byte (actually the same as above, since PC increment is suppressed. Also discarded.)
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Push((uint16_t)(PC()));
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if(_needNmi) {
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_needNmi = false;
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Push((uint8_t)(PS() | PSFlags::Reserved));
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SetFlags(PSFlags::Interrupt);
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SetPC(MemoryReadWord(CPU::NMIVector));
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#ifndef DUMMYCPU
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_console->DebugAddTrace("NMI");
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_console->DebugProcessInterrupt(originalPc, _state.PC, true);
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#endif
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} else {
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Push((uint8_t)(PS() | PSFlags::Reserved));
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SetFlags(PSFlags::Interrupt);
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SetPC(MemoryReadWord(CPU::IRQVector));
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#ifndef DUMMYCPU
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_console->DebugAddTrace("IRQ");
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_console->DebugProcessInterrupt(originalPc, _state.PC, false);
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#endif
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}
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}
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void CPU::BRK() {
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Push((uint16_t)(PC() + 1));
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uint8_t flags = PS() | PSFlags::Break | PSFlags::Reserved;
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if(_needNmi) {
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_needNmi = false;
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Push((uint8_t)flags);
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SetFlags(PSFlags::Interrupt);
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SetPC(MemoryReadWord(CPU::NMIVector));
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#ifndef DUMMYCPU
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_console->DebugAddTrace("NMI");
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#endif
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} else {
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Push((uint8_t)flags);
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SetFlags(PSFlags::Interrupt);
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SetPC(MemoryReadWord(CPU::IRQVector));
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#ifndef DUMMYCPU
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_console->DebugAddTrace("IRQ");
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#endif
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}
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//Ensure we don't start an NMI right after running a BRK instruction (first instruction in IRQ handler must run first - needed for nmi_and_brk test)
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_prevNeedNmi = false;
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}
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void CPU::MemoryWrite(uint16_t addr, uint8_t value, MemoryOperationType operationType)
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{
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#ifdef DUMMYCPU
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if(operationType == MemoryOperationType::Write || operationType == MemoryOperationType::DummyWrite) {
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_writeAddresses[_writeCounter] = addr;
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_isDummyWrite[_writeCounter] = operationType == MemoryOperationType::DummyWrite;
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_writeValue[_writeCounter] = value;
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_writeCounter++;
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}
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#else
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_cpuWrite = true;
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StartCpuCycle(false);
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_memoryManager->Write(addr, value, operationType);
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EndCpuCycle(false);
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_cpuWrite = false;
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#endif
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}
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uint8_t CPU::MemoryRead(uint16_t addr, MemoryOperationType operationType) {
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#ifdef DUMMYCPU
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uint8_t value = _memoryManager->DebugRead(addr);
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if(operationType == MemoryOperationType::Read || operationType == MemoryOperationType::DummyRead) {
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_readAddresses[_readCounter] = addr;
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_readValue[_readCounter] = value;
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_isDummyRead[_readCounter] = operationType == MemoryOperationType::DummyRead;
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_readCounter++;
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}
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return value;
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#else
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ProcessPendingDma(addr);
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StartCpuCycle(true);
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uint8_t value = _memoryManager->Read(addr, operationType);
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EndCpuCycle(true);
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return value;
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#endif
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}
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uint16_t CPU::FetchOperand()
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{
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switch(_instAddrMode) {
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case AddrMode::Acc:
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case AddrMode::Imp: DummyRead(); return 0;
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case AddrMode::Imm:
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case AddrMode::Rel: return GetImmediate();
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case AddrMode::Zero: return GetZeroAddr();
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case AddrMode::ZeroX: return GetZeroXAddr();
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case AddrMode::ZeroY: return GetZeroYAddr();
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case AddrMode::Ind: return GetIndAddr();
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case AddrMode::IndX: return GetIndXAddr();
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case AddrMode::IndY: return GetIndYAddr(false);
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case AddrMode::IndYW: return GetIndYAddr(true);
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case AddrMode::Abs: return GetAbsAddr();
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case AddrMode::AbsX: return GetAbsXAddr(false);
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case AddrMode::AbsXW: return GetAbsXAddr(true);
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case AddrMode::AbsY: return GetAbsYAddr(false);
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case AddrMode::AbsYW: return GetAbsYAddr(true);
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default: break;
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}
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#if !defined(LIBRETRO) && !defined(DUMMYCPU)
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if(_lastCrashWarning == 0 || _cycleCount - _lastCrashWarning > 5000000) {
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MessageManager::DisplayMessage("Error", "GameCrash", "Invalid OP code - CPU crashed.");
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_lastCrashWarning = _cycleCount;
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}
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if(_console->GetSettings()->CheckFlag(EmulationFlags::BreakOnCrash)) {
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//When "Break on Crash" is enabled, open the debugger and break immediately if a crash occurs
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_console->GetDebugger(true)->BreakImmediately(BreakSource::BreakOnCpuCrash);
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}
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if(_console->IsNsf()) {
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//Don't stop emulation on CPU crash when playing NSFs, reset cpu instead
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_console->Reset(true);
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return 0;
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} else {
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return 0;
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}
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#else
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return 0;
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#endif
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}
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void CPU::EndCpuCycle(bool forRead)
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{
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_masterClock += forRead ? (_endClockCount + 1) : (_endClockCount - 1);
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_console->GetPpu()->Run(_masterClock - _ppuOffset);
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//"The internal signal goes high during φ1 of the cycle that follows the one where the edge is detected,
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//and stays high until the NMI has been handled. "
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_prevNeedNmi = _needNmi;
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//"This edge detector polls the status of the NMI line during φ2 of each CPU cycle (i.e., during the
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//second half of each cycle) and raises an internal signal if the input goes from being high during
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//one cycle to being low during the next"
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if(!_prevNmiFlag && _state.NMIFlag) {
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_needNmi = true;
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}
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_prevNmiFlag = _state.NMIFlag;
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//"it's really the status of the interrupt lines at the end of the second-to-last cycle that matters."
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//Keep the irq lines values from the previous cycle. The before-to-last cycle's values will be used
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_prevRunIrq = _runIrq;
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_runIrq = ((_state.IRQFlag & _irqMask) > 0 && !CheckFlag(PSFlags::Interrupt));
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}
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void CPU::StartCpuCycle(bool forRead)
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{
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_masterClock += forRead ? (_startClockCount - 1) : (_startClockCount + 1);
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_cycleCount++;
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_console->GetPpu()->Run(_masterClock - _ppuOffset);
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_console->ProcessCpuClock();
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}
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void CPU::ProcessPendingDma(uint16_t readAddress)
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{
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if(!_needHalt) {
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return;
|
|
}
|
|
|
|
//"If this cycle is a read, hijack the read, discard the value, and prevent all other actions that occur on this cycle (PC not incremented, etc)"
|
|
StartCpuCycle(true);
|
|
_memoryManager->Read(readAddress, MemoryOperationType::DummyRead);
|
|
EndCpuCycle(true);
|
|
_needHalt = false;
|
|
|
|
uint16_t spriteDmaCounter = 0;
|
|
uint8_t spriteReadAddr = 0;
|
|
uint8_t readValue = 0;
|
|
bool skipDummyReads = (readAddress == 0x4016 || readAddress == 0x4017);
|
|
|
|
auto processCycle = [this] {
|
|
//Sprite DMA cycles count as halt/dummy cycles for the DMC DMA when both run at the same time
|
|
if(_needHalt) {
|
|
_needHalt = false;
|
|
} else if(_needDummyRead) {
|
|
_needDummyRead = false;
|
|
}
|
|
StartCpuCycle(true);
|
|
};
|
|
|
|
while(_dmcDmaRunning || _spriteDmaTransfer) {
|
|
bool getCycle = (_cycleCount & 0x01) == 0;
|
|
if(getCycle) {
|
|
if(_dmcDmaRunning && !_needHalt && !_needDummyRead) {
|
|
//DMC DMA is ready to read a byte (both halt and dummy read cycles were performed before this)
|
|
processCycle();
|
|
readValue = _memoryManager->Read(_console->GetApu()->GetDmcReadAddress(), MemoryOperationType::DmcRead);
|
|
EndCpuCycle(true);
|
|
_console->GetApu()->SetDmcReadBuffer(readValue);
|
|
_dmcDmaRunning = false;
|
|
} else if(_spriteDmaTransfer) {
|
|
//DMC DMA is not running, or not ready, run sprite DMA
|
|
processCycle();
|
|
readValue = _memoryManager->Read(_spriteDmaOffset * 0x100 + spriteReadAddr);
|
|
EndCpuCycle(true);
|
|
spriteReadAddr++;
|
|
spriteDmaCounter++;
|
|
} else {
|
|
//DMC DMA is running, but not ready (need halt/dummy read) and sprite DMA isn't runnnig, perform a dummy read
|
|
assert(_needHalt || _needDummyRead);
|
|
processCycle();
|
|
if(!skipDummyReads) {
|
|
_memoryManager->Read(readAddress, MemoryOperationType::DummyRead);
|
|
}
|
|
EndCpuCycle(true);
|
|
}
|
|
} else {
|
|
if(_spriteDmaTransfer && (spriteDmaCounter & 0x01)) {
|
|
//Sprite DMA write cycle (only do this if a sprite dma read was performed last cycle)
|
|
processCycle();
|
|
_memoryManager->Write(0x2004, readValue, MemoryOperationType::Write);
|
|
EndCpuCycle(true);
|
|
spriteDmaCounter++;
|
|
if(spriteDmaCounter == 0x200) {
|
|
_spriteDmaTransfer = false;
|
|
}
|
|
} else {
|
|
//Align to read cycle before starting sprite DMA (or align to perform DMC read)
|
|
processCycle();
|
|
if(!skipDummyReads) {
|
|
_memoryManager->Read(readAddress, MemoryOperationType::DummyRead);
|
|
}
|
|
EndCpuCycle(true);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void CPU::RunDMATransfer(uint8_t offsetValue)
|
|
{
|
|
_spriteDmaTransfer = true;
|
|
_spriteDmaOffset = offsetValue;
|
|
_needHalt = true;
|
|
}
|
|
|
|
void CPU::StartDmcTransfer()
|
|
{
|
|
_dmcDmaRunning = true;
|
|
_needDummyRead = true;
|
|
_needHalt = true;
|
|
}
|
|
|
|
uint32_t CPU::GetClockRate(NesModel model)
|
|
{
|
|
switch(model) {
|
|
default:
|
|
case NesModel::NTSC: return CPU::ClockRateNtsc; break;
|
|
case NesModel::PAL: return CPU::ClockRatePal; break;
|
|
case NesModel::Dendy: return CPU::ClockRateDendy; break;
|
|
}
|
|
}
|
|
|
|
void CPU::SetMasterClockDivider(NesModel region)
|
|
{
|
|
switch(region) {
|
|
default:
|
|
case NesModel::NTSC:
|
|
_startClockCount = 6;
|
|
_endClockCount = 6;
|
|
break;
|
|
|
|
case NesModel::PAL:
|
|
_startClockCount = 8;
|
|
_endClockCount = 8;
|
|
break;
|
|
|
|
case NesModel::Dendy:
|
|
_startClockCount = 7;
|
|
_endClockCount = 8;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void CPU::StreamState(bool saving)
|
|
{
|
|
EmulationSettings* settings = _console->GetSettings();
|
|
uint32_t extraScanlinesBeforeNmi = settings->GetPpuExtraScanlinesBeforeNmi();
|
|
uint32_t extraScanlinesAfterNmi = settings->GetPpuExtraScanlinesAfterNmi();
|
|
uint32_t dipSwitches = _console->GetSettings()->GetDipSwitches();
|
|
|
|
Stream(_state.PC, _state.SP, _state.PS, _state.A, _state.X, _state.Y, _cycleCount, _state.NMIFlag,
|
|
_state.IRQFlag, _dmcDmaRunning, _spriteDmaTransfer,
|
|
extraScanlinesBeforeNmi, extraScanlinesAfterNmi, dipSwitches,
|
|
_needDummyRead, _needHalt, _startClockCount, _endClockCount, _ppuOffset, _masterClock,
|
|
_prevNeedNmi, _prevNmiFlag, _needNmi);
|
|
|
|
if(!saving) {
|
|
settings->SetPpuNmiConfig(extraScanlinesBeforeNmi, extraScanlinesAfterNmi);
|
|
settings->SetDipSwitches(dipSwitches);
|
|
}
|
|
}
|