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https://github.com/SourMesen/Mesen.git
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380 lines
10 KiB
C++
380 lines
10 KiB
C++
#pragma once
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#include "stdafx.h"
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#include "BaseMapper.h"
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class Fk23C : public BaseMapper
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{
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private:
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uint8_t _prgBankingMode;
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uint8_t _outerChrBankSize;
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bool _selectChrRam;
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bool _mmc3ChrMode;
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bool _cnromChrMode;
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uint16_t _prgBaseBits;
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uint8_t _chrBaseBits;
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bool _extendedMmc3Mode;
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uint8_t _wramBankSelect;
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bool _ramInFirstChrBank;
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bool _allowSingleScreenMirroring;
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bool _fk23RegistersEnabled;
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bool _wramConfigEnabled;
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bool _wramEnabled;
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bool _wramWriteProtected;
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bool _invertPrgA14;
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bool _invertChrA12;
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uint8_t _currentRegister;
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uint8_t _irqReloadValue;
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uint8_t _irqCounter;
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bool _irqReload;
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bool _irqEnabled;
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uint8_t _mirroringReg;
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uint8_t _cnromChrReg;
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uint8_t _mmc3Registers[12];
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uint8_t _irqDelay;
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A12Watcher _a12Watcher;
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protected:
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uint16_t GetPRGPageSize() override { return 0x2000; }
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uint16_t GetCHRPageSize() override { return 0x0400; }
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uint32_t GetChrRamSize() override { return 0x40000; } //Some games have up to 256kb of CHR RAM (only used for iNES 1.0 files w/ no DB entry)
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uint16_t GetChrRamPageSize() override { return 0x400; }
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uint32_t GetWorkRamSize() override { return 0x8000; } //Somes games have up to 32kb of Work RAM (only used for iNES 1.0 files w/ no DB entry)
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uint32_t GetWorkRamPageSize() override { return 0x2000; }
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void InitMapper() override
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{
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//$5000
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_prgBankingMode = 0;
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_outerChrBankSize = 0;
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_selectChrRam = false;
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_mmc3ChrMode = true;
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//$5001 (mostly)
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//Subtype 1, 1024 KiB PRG-ROM, 1024 KiB CHR-ROM: boot in second 512 KiB of PRG-ROM.
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_prgBaseBits = (_prgSize == 1024*1024 && _prgSize == _chrRomSize) ? 0x20 : 0;
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//$5002
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_chrBaseBits = 0;
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//$5003
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_extendedMmc3Mode = false;
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_cnromChrMode = false;
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//$A001
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_wramBankSelect = 0;
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_ramInFirstChrBank = false;
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_allowSingleScreenMirroring = false;
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_wramConfigEnabled = false;
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_fk23RegistersEnabled = false;
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_wramEnabled = false;
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_wramWriteProtected = false;
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_currentRegister = 0;
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_cnromChrReg = 0;
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constexpr uint8_t initValues[12] = { 0,2,4,5,6,7,0,1,0xFE, 0xFF, 0xFF, 0xFF };
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for(int i = 0; i < 12; i++) {
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_mmc3Registers[i] = initValues[i];
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}
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_invertPrgA14 = false;
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_invertChrA12 = false;
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_mirroringReg = 0;
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_irqCounter = 0;
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_irqEnabled = false;
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_irqReload = false;
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_irqReloadValue = 0;
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_irqDelay = 0;
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AddRegisterRange(0x5000, 0x5FFF, MemoryOperation::Write);
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UpdateState();
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}
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void Reset(bool softReset) override
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{
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if(softReset) {
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if(_wramConfigEnabled && _selectChrRam && HasBattery()) {
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_prgBaseBits = 0;
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UpdateState();
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}
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}
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}
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void StreamState(bool saving) override
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{
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SnapshotInfo a12Watcher { &_a12Watcher };
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ArrayInfo<uint8_t> regs { _mmc3Registers, 12 };
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Stream(
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_prgBankingMode, _outerChrBankSize, _selectChrRam, _mmc3ChrMode, _cnromChrMode, _prgBaseBits, _chrBaseBits, _extendedMmc3Mode,
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_wramBankSelect, _ramInFirstChrBank, _allowSingleScreenMirroring, _fk23RegistersEnabled, _wramConfigEnabled, _wramEnabled, _wramWriteProtected,
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_invertPrgA14, _invertChrA12, _currentRegister, _irqReloadValue,_irqCounter, _irqReload, _irqEnabled, _mirroringReg, _cnromChrReg,
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_irqDelay, regs, a12Watcher
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);
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if(!saving) {
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UpdateState();
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}
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}
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void SelectCHRPage(uint16_t slot, uint16_t page, ChrMemoryType memoryType = ChrMemoryType::Default) override
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{
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bool useChrRam = !HasChrRom() || (_selectChrRam && _chrRamSize > 0) || (_wramConfigEnabled && _ramInFirstChrBank && page <= 7);
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BaseMapper::SelectCHRPage(slot, page, useChrRam ? ChrMemoryType::ChrRam : ChrMemoryType::ChrRom);
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}
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void UpdatePrg()
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{
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switch(_prgBankingMode) {
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case 0:
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case 1:
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case 2:
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if(_extendedMmc3Mode) {
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uint8_t swap = _invertPrgA14 ? 2 : 0;
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uint16_t outer = (_prgBaseBits << 1);
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SelectPRGPage(0 ^ swap, _mmc3Registers[6] | outer);
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SelectPRGPage(1, _mmc3Registers[7] | outer);
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SelectPRGPage(2 ^ swap, _mmc3Registers[8] | outer);
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SelectPRGPage(3, _mmc3Registers[9] | outer);
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} else {
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uint8_t swap = _invertPrgA14 ? 2 : 0;
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uint8_t innerMask = 0x3F >> _prgBankingMode;
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uint16_t outer = (_prgBaseBits << 1) & ~innerMask;
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SelectPRGPage(0 ^ swap, (_mmc3Registers[6] & innerMask) | outer);
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SelectPRGPage(1, (_mmc3Registers[7] & innerMask) | outer);
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SelectPRGPage(2 ^ swap, (0xFE & innerMask) | outer);
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SelectPRGPage(3, (0xFF & innerMask) | outer);
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}
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break;
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case 3:
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SelectPrgPage2x(0, _prgBaseBits << 1);
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SelectPrgPage2x(1, _prgBaseBits << 1);
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break;
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case 4:
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SelectPrgPage4x(0, (_prgBaseBits & 0xFFE) << 1);
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break;
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default:
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break;
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}
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}
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void UpdateChr()
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{
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if(!_mmc3ChrMode) {
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uint16_t innerMask = _cnromChrMode ? (_outerChrBankSize ? 1 : 3) : 0;
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for(int i = 0; i < 8; i++) {
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SelectCHRPage(i, (((_cnromChrReg & innerMask) | _chrBaseBits) << 3) + i);
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}
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} else {
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uint8_t swap = _invertChrA12 ? 0x04 : 0;
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if(_extendedMmc3Mode) {
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uint16_t outer = (_chrBaseBits << 3);
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SelectCHRPage(0 ^ swap, _mmc3Registers[0] | outer);
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SelectCHRPage(1 ^ swap, _mmc3Registers[10] | outer);
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SelectCHRPage(2 ^ swap, _mmc3Registers[1] | outer);
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SelectCHRPage(3 ^ swap, _mmc3Registers[11] | outer);
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SelectCHRPage(4 ^ swap, _mmc3Registers[2] | outer);
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SelectCHRPage(5 ^ swap, _mmc3Registers[3] | outer);
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SelectCHRPage(6 ^ swap, _mmc3Registers[4] | outer);
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SelectCHRPage(7 ^ swap, _mmc3Registers[5] | outer);
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} else {
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uint8_t innerMask = (_outerChrBankSize ? 0x7F : 0xFF);
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uint16_t outer = (_chrBaseBits << 3) & ~innerMask;
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SelectCHRPage(0 ^ swap, ((_mmc3Registers[0] & 0xFE) & innerMask) | outer);
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SelectCHRPage(1 ^ swap, ((_mmc3Registers[0] | 0x01) & innerMask) | outer);
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SelectCHRPage(2 ^ swap, ((_mmc3Registers[1] & 0xFE) & innerMask) | outer);
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SelectCHRPage(3 ^ swap, ((_mmc3Registers[1] | 0x01) & innerMask) | outer);
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SelectCHRPage(4 ^ swap, (_mmc3Registers[2] & innerMask) | outer);
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SelectCHRPage(5 ^ swap, (_mmc3Registers[3] & innerMask) | outer);
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SelectCHRPage(6 ^ swap, (_mmc3Registers[4] & innerMask) | outer);
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SelectCHRPage(7 ^ swap, (_mmc3Registers[5] & innerMask) | outer);
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}
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}
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}
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void UpdateState()
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{
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switch(_mirroringReg & (_allowSingleScreenMirroring ? 0x03 : 0x01)) {
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case 0: SetMirroringType(MirroringType::Vertical); break;
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case 1: SetMirroringType(MirroringType::Horizontal); break;
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case 2: SetMirroringType(MirroringType::ScreenAOnly); break;
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case 3: SetMirroringType(MirroringType::ScreenBOnly); break;
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}
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UpdatePrg();
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UpdateChr();
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if(_wramConfigEnabled) {
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uint8_t nextBank = (_wramBankSelect + 1) & 0x03;
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SetCpuMemoryMapping(0x4000, 0x5FFF, nextBank, HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam, MemoryAccessType::ReadWrite);
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SetCpuMemoryMapping(0x6000, 0x7FFF, _wramBankSelect, HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam, MemoryAccessType::ReadWrite);
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} else {
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if(_wramEnabled) {
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SetCpuMemoryMapping(0x6000, 0x7FFF, 0, PrgMemoryType::WorkRam, _wramWriteProtected ? MemoryAccessType::Read : MemoryAccessType::ReadWrite);
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} else {
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RemoveCpuMemoryMapping(0x6000, 0x7FFF);
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}
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RemoveCpuMemoryMapping(0x4000, 0x5FFF);
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};
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}
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void WriteRegister(uint16_t addr, uint8_t value) override
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{
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if(addr < 0x8000) {
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if(_fk23RegistersEnabled || !_wramConfigEnabled) {
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uint16_t mask = 0x5010;
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if((addr & mask) != mask) {
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//not a register
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return;
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}
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switch(addr & 0x03) {
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case 0:
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_prgBankingMode = value & 0x07;
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_outerChrBankSize = (value & 0x10) >> 4;
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_selectChrRam = (value & 0x20) != 0;
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_mmc3ChrMode = (value & 0x40) == 0;
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_prgBaseBits = (_prgBaseBits & ~0x180) | ((value & 0x80) << 1) | ((value & 0x08) << 4);
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break;
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case 1:
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_prgBaseBits = (_prgBaseBits & ~0x7F) | (value & 0x7F);
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break;
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case 2:
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_prgBaseBits = (_prgBaseBits & ~0x200) | ((value & 0x40) << 3);
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_chrBaseBits = value;
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_cnromChrReg = 0;
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break;
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case 3:
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_extendedMmc3Mode = (value & 0x02) != 0;
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_cnromChrMode = (value & 0x44) != 0;
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break;
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}
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UpdateState();
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} else {
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//FK23C Registers disabled, $5000-$5FFF maps to the second 4 KiB of the 8 KiB WRAM bank 2
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WritePrgRam(addr, value);
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}
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} else {
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if(_cnromChrMode && (addr <= 0x9FFF || addr >= 0xC000)) {
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_cnromChrReg = value & 0x03;
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UpdateState();
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}
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switch(addr & 0xE001) {
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case 0x8000:
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if(_prgSize == 16384*1024 && (value == 0x46 || value == 0x47)) {
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//Subtype 2, 16384 KiB PRG-ROM, no CHR-ROM: Like Subtype 0, but MMC3 registers $46 and $47 swapped.
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value ^= 1;
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}
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_invertPrgA14 = (value & 0x40) != 0;
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_invertChrA12 = (value & 0x80) != 0;
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_currentRegister = value & 0x0F;
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UpdateState();
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break;
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case 0x8001: {
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uint8_t reg = _currentRegister & (_extendedMmc3Mode ? 0x0F : 0x07);
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if(reg < 12) {
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_mmc3Registers[_currentRegister & (_extendedMmc3Mode ? 0x0F : 0x07)] = value;
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UpdateState();
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}
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break;
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}
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case 0xA000:
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_mirroringReg = value & 0x03;
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UpdateState();
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break;
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case 0xA001:
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if((value & 0x20) == 0) {
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//Ignore extra bits if bit 5 is not set
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value &= 0xC0;
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}
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_wramBankSelect = (value & 0x03);
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_ramInFirstChrBank = (value & 0x04) != 0;
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_allowSingleScreenMirroring = (value & 0x08) != 0;
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_wramConfigEnabled = (value & 0x20) != 0;
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_fk23RegistersEnabled = (value & 0x40) != 0;
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_wramWriteProtected = (value & 0x40) != 0;
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_wramEnabled = (value & 0x80) != 0;
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UpdateState();
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break;
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case 0xC000:
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_irqReloadValue = value;
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break;
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case 0xC001:
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_irqCounter = 0;
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_irqReload = true;
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break;
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case 0xE000:
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_irqEnabled = false;
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_console->GetCpu()->ClearIrqSource(IRQSource::External);
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break;
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case 0xE001:
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_irqEnabled = true;
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break;
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}
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}
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}
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public:
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void ProcessCpuClock() override
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{
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if(_irqDelay > 0) {
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_irqDelay--;
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if(_irqDelay == 0) {
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_console->GetCpu()->SetIrqSource(IRQSource::External);
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}
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}
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}
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void NotifyVRAMAddressChange(uint16_t addr) override
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{
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switch(_a12Watcher.UpdateVramAddress(addr, _console->GetPpu()->GetFrameCycle())) {
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case A12StateChange::None:
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case A12StateChange::Fall:
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break;
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case A12StateChange::Rise:
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if(_irqCounter == 0 || _irqReload) {
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_irqCounter = _irqReloadValue;
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} else {
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_irqCounter--;
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}
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if(_irqCounter == 0 && _irqEnabled) {
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_irqDelay = 2;
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}
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_irqReload = false;
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break;
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}
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}
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}; |