mirror of
https://github.com/SourMesen/Mesen.git
synced 2024-05-20 05:01:03 -04:00
670 lines
21 KiB
C++
670 lines
21 KiB
C++
#pragma once
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#include "stdafx.h"
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#include "BaseMapper.h"
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#include "PPU.h"
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#include "MMC5Audio.h"
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#include "MMC5MemoryHandler.h"
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class MMC5 : public BaseMapper
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{
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private:
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static constexpr int ExRamSize = 0x400;
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static constexpr uint8_t NtWorkRamIndex = 4;
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static constexpr uint8_t NtEmptyIndex = 2;
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static constexpr uint8_t NtFillModeIndex = 3;
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unique_ptr<MMC5Audio> _audio;
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unique_ptr<MMC5MemoryHandler> _mmc5MemoryHandler;
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uint8_t _prgRamProtect1;
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uint8_t _prgRamProtect2;
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uint8_t _fillModeTile;
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uint8_t _fillModeColor;
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bool _verticalSplitEnabled;
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bool _verticalSplitRightSide;
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uint8_t _verticalSplitDelimiterTile;
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uint8_t _verticalSplitScroll;
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uint8_t _verticalSplitBank;
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bool _splitInSplitRegion;
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uint32_t _splitVerticalScroll;
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uint32_t _splitTile;
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int32_t _splitTileNumber;
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uint8_t _multiplierValue1;
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uint8_t _multiplierValue2;
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uint8_t _nametableMapping;
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uint8_t _extendedRamMode;
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//Extended attribute mode fields (used when _extendedRamMode == 1)
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uint16_t _exAttributeLastNametableFetch;
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int8_t _exAttrLastFetchCounter;
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uint8_t _exAttrSelectedChrBank;
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uint8_t _prgMode;
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uint8_t _prgBanks[5];
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//CHR-related fields
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uint8_t _chrMode;
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uint8_t _chrUpperBits;
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uint16_t _chrBanks[12];
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uint16_t _lastChrReg;
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bool _prevChrA;
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//IRQ counter related fields
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uint8_t _irqCounterTarget;
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bool _irqEnabled;
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uint8_t _scanlineCounter;
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bool _irqPending;
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bool _needInFrame;
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bool _ppuInFrame;
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uint8_t _ppuIdleCounter;
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uint16_t _lastPpuReadAddr;
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uint8_t _ntReadCounter;
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void SwitchPrgBank(uint16_t reg, uint8_t value)
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{
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_prgBanks[reg - 0x5113] = value;
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UpdatePrgBanks();
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}
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void GetCpuBankInfo(uint16_t reg, uint8_t &bankNumber, PrgMemoryType &memoryType, uint8_t &accessType)
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{
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bankNumber = _prgBanks[reg-0x5113];
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memoryType = PrgMemoryType::PrgRom;
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if((((bankNumber & 0x80) == 0x00) && reg != 0x5117) || reg == 0x5113) {
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bankNumber &= 0x07;
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accessType = MemoryAccessType::Read;
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if(_prgRamProtect1 == 0x02 && _prgRamProtect2 == 0x01) {
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accessType |= MemoryAccessType::Write;
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}
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// WRAM/SRAM mirroring logic (only supports existing/known licensed MMC5 boards)
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// Bank number
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// 0 1 2 3 4 5 6 7
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// --------------------------
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// None : - - - - - - - -
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// 1x 8kb : 0 0 0 0 - - - -
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// 2x 8kb : 0 0 0 0 1 1 1 1
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// 1x 32kb : 0 1 2 3 - - - -
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int32_t realWorkRamSize = _workRamSize - (HasBattery() ? 0 : MMC5::ExRamSize);
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int32_t realSaveRamSize = _saveRamSize - (!HasBattery() ? 0 : MMC5::ExRamSize);
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if(IsNes20() || _romInfo.IsInDatabase) {
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memoryType = PrgMemoryType::WorkRam;
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if(HasBattery() && (bankNumber <= 3 || realSaveRamSize > 0x2000)) {
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memoryType = PrgMemoryType::SaveRam;
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}
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if(realSaveRamSize + realWorkRamSize != 0x4000 && bankNumber >= 4) {
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//When not 2x 8kb (=16kb), banks 4/5/6/7 select the empty socket and return open bus
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accessType = MemoryAccessType::NoAccess;
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}
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} else {
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memoryType = HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam;
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}
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if(memoryType == PrgMemoryType::WorkRam) {
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//Properly mirror work ram (by ignoring the extra 1kb ExRAM section)
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bankNumber &= (realWorkRamSize / 0x2000) - 1;
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if(_workRamSize == MMC5::ExRamSize) {
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accessType = MemoryAccessType::NoAccess;
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}
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} else if(memoryType == PrgMemoryType::SaveRam) {
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//Properly mirror work ram (by ignoring the extra 1kb ExRAM section)
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bankNumber &= (realSaveRamSize / 0x2000) - 1;
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if(_saveRamSize == MMC5::ExRamSize) {
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accessType = MemoryAccessType::NoAccess;
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}
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}
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} else {
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accessType = MemoryAccessType::Read;
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bankNumber &= 0x7F;
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}
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}
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void UpdatePrgBanks()
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{
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uint8_t value;
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PrgMemoryType memoryType;
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uint8_t accessType;
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GetCpuBankInfo(0x5113, value, memoryType, accessType);
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SetCpuMemoryMapping(0x6000, 0x7FFF, value, memoryType, accessType);
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//PRG Bank 0
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//Mode 0,1,2 - Ignored
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//Mode 3 - Select an 8KB PRG bank at $8000-$9FFF
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if(_prgMode == 3) {
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GetCpuBankInfo(0x5114, value, memoryType, accessType);
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SetCpuMemoryMapping(0x8000, 0x9FFF, value, memoryType, accessType);
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}
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//PRG Bank 1
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//Mode 0 - Ignored
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//Mode 1,2 - Select a 16KB PRG bank at $8000-$BFFF (ignore bottom bit)
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//Mode 3 - Select an 8KB PRG bank at $A000-$BFFF
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GetCpuBankInfo(0x5115, value, memoryType, accessType);
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if(_prgMode == 1 || _prgMode == 2) {
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SetCpuMemoryMapping(0x8000, 0xBFFF, value & 0xFE, memoryType, accessType);
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} else if(_prgMode == 3) {
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SetCpuMemoryMapping(0xA000, 0xBFFF, value, memoryType, accessType);
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}
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//Mode 0,1 - Ignored
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//Mode 2,3 - Select an 8KB PRG bank at $C000-$DFFF
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if(_prgMode == 2 || _prgMode == 3) {
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GetCpuBankInfo(0x5116, value, memoryType, accessType);
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SetCpuMemoryMapping(0xC000, 0xDFFF, value, memoryType, accessType);
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}
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//Mode 0 - Select a 32KB PRG ROM bank at $8000-$FFFF (ignore bottom 2 bits)
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//Mode 1 - Select a 16KB PRG ROM bank at $C000-$FFFF (ignore bottom bit)
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//Mode 2,3 - Select an 8KB PRG ROM bank at $E000-$FFFF
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GetCpuBankInfo(0x5117, value, memoryType, accessType);
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if(_prgMode == 0) {
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SetCpuMemoryMapping(0x8000, 0xFFFF, value & 0x7C, memoryType, accessType);
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} else if(_prgMode == 1) {
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SetCpuMemoryMapping(0xC000, 0xFFFF, value & 0x7E, memoryType, accessType);
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} else if(_prgMode == 2 || _prgMode == 3) {
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SetCpuMemoryMapping(0xE000, 0xFFFF, value & 0x7F, memoryType, accessType);
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}
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}
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void SwitchChrBank(uint16_t reg, uint8_t value)
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{
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uint16_t newValue = value | (_chrUpperBits << 8);
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if(newValue != _chrBanks[reg - 0x5120] || _lastChrReg != reg) {
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_chrBanks[reg - 0x5120] = newValue;
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_lastChrReg = reg;
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UpdateChrBanks(true);
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}
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}
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void UpdateChrBanks(bool forceUpdate)
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{
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bool largeSprites = (_mmc5MemoryHandler->GetReg(0x2000) & 0x20) != 0;
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if(!largeSprites) {
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//Using 8x8 sprites resets the last written to bank logic
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_lastChrReg = 0;
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}
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bool chrA = !largeSprites || (_splitTileNumber >= 32 && _splitTileNumber < 40) || (!_ppuInFrame && _lastChrReg <= 0x5127);
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if(!forceUpdate && chrA == _prevChrA) {
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return;
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}
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_prevChrA = chrA;
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if(_chrMode == 0) {
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SelectChrPage8x(0, _chrBanks[chrA ? 0x07 : 0x0B] << 3);
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} else if(_chrMode == 1) {
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SelectChrPage4x(0, _chrBanks[chrA ? 0x03 : 0x0B] << 2);
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SelectChrPage4x(1, _chrBanks[chrA ? 0x07 : 0x0B] << 2);
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} else if(_chrMode == 2) {
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SelectChrPage2x(0, _chrBanks[chrA ? 0x01 : 0x09] << 1);
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SelectChrPage2x(1, _chrBanks[chrA ? 0x03 : 0x0B] << 1);
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SelectChrPage2x(2, _chrBanks[chrA ? 0x05 : 0x09] << 1);
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SelectChrPage2x(3, _chrBanks[chrA ? 0x07 : 0x0B] << 1);
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} else if(_chrMode == 3) {
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SelectCHRPage(0, _chrBanks[chrA ? 0x00 : 0x08]);
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SelectCHRPage(1, _chrBanks[chrA ? 0x01 : 0x09]);
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SelectCHRPage(2, _chrBanks[chrA ? 0x02 : 0x0A]);
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SelectCHRPage(3, _chrBanks[chrA ? 0x03 : 0x0B]);
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SelectCHRPage(4, _chrBanks[chrA ? 0x04 : 0x08]);
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SelectCHRPage(5, _chrBanks[chrA ? 0x05 : 0x09]);
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SelectCHRPage(6, _chrBanks[chrA ? 0x06 : 0x0A]);
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SelectCHRPage(7, _chrBanks[chrA ? 0x07 : 0x0B]);
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}
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}
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void ProcessCpuClock() override
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{
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_audio->Clock();
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if(_ppuIdleCounter) {
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_ppuIdleCounter--;
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if(_ppuIdleCounter == 0) {
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//"The "in-frame" flag is cleared when the PPU is no longer rendering. This is detected when 3 CPU cycles pass without a PPU read having occurred (PPU /RD has not been low during the last 3 M2 rises)."
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_ppuInFrame = false;
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UpdateChrBanks(true);
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}
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}
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}
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void SetNametableMapping(uint8_t value)
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{
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_nametableMapping = value;
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uint8_t nametables[4] = {
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0, //"0 - On-board VRAM page 0"
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1, //"1 - On-board VRAM page 1"
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_extendedRamMode <= 1 ? NtWorkRamIndex : NtEmptyIndex, //"2 - Internal Expansion RAM, only if the Extended RAM mode allows it ($5104 is 00/01); otherwise, the nametable will read as all zeros,"
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NtFillModeIndex //"3 - Fill-mode data"
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};
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for(int i = 0; i < 4; i++) {
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uint8_t nametableId = nametables[(value >> (i * 2)) & 0x03];
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if(nametableId == NtWorkRamIndex) {
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uint8_t* source = HasBattery() ? (_saveRam + (_saveRamSize - MMC5::ExRamSize)) : (_workRam + (_workRamSize - MMC5::ExRamSize));
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SetPpuMemoryMapping(0x2000+i*0x400, 0x2000+i*0x400+0x3FF, source, MemoryAccessType::ReadWrite);
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} else {
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SetNametable(i, nametableId);
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}
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}
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}
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void SetExtendedRamMode(uint8_t mode)
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{
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_extendedRamMode = mode;
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MemoryAccessType accessType;
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if(_extendedRamMode <= 1) {
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//"Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)"
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//See overridden WriteRam function for implementation
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accessType = MemoryAccessType::Write;
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} else if(_extendedRamMode == 2) {
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//"Mode 2 - Readable and writable"
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accessType = MemoryAccessType::ReadWrite;
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} else {
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//"Mode 3 - Read-only"
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accessType = MemoryAccessType::Read;
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}
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if(HasBattery()) {
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SetCpuMemoryMapping(0x5C00, 0x5FFF, PrgMemoryType::SaveRam, _saveRamSize - MMC5::ExRamSize, accessType);
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} else {
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SetCpuMemoryMapping(0x5C00, 0x5FFF, PrgMemoryType::WorkRam, _workRamSize - MMC5::ExRamSize, accessType);
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}
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SetNametableMapping(_nametableMapping);
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}
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void SetFillModeTile(uint8_t tile)
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{
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_fillModeTile = tile;
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memset(GetNametable(NtFillModeIndex), tile, 32 * 30); //32 tiles per row, 30 rows
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}
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void SetFillModeColor(uint8_t color)
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{
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_fillModeColor = color;
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uint8_t attributeByte = color | color << 2 | color << 4 | color << 6;
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memset(GetNametable(NtFillModeIndex) + 32 * 30, attributeByte, 64); //Attribute table is 64 bytes
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}
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protected:
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virtual uint16_t GetPRGPageSize() override { return 0x2000; }
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virtual uint16_t GetCHRPageSize() override { return 0x400; }
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virtual uint16_t RegisterStartAddress() override { return 0x5000; }
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virtual uint16_t RegisterEndAddress() override { return 0x5206; }
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virtual uint32_t GetSaveRamPageSize() override { return 0x2000; }
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virtual uint32_t GetWorkRamPageSize() override { return 0x2000; }
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virtual bool ForceSaveRamSize() override { return true; }
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virtual bool ForceWorkRamSize() override { return true; }
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virtual uint32_t GetSaveRamSize() override
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{
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uint32_t size;
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if(IsNes20()) {
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size = _romInfo.NesHeader.GetSaveRamSize();
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} else if(_romInfo.IsInDatabase) {
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size = _romInfo.DatabaseInfo.SaveRamSize;
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} else {
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//Emulate as if a single 64k block of work/save ram existed
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size = _romInfo.HasBattery ? 0x10000 : 0;
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}
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if(HasBattery()) {
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//If there's a battery on the board, exram gets saved, too.
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size += MMC5::ExRamSize;
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}
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return size;
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}
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virtual uint32_t GetWorkRamSize() override
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{
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uint32_t size;
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if(IsNes20()) {
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size = _romInfo.NesHeader.GetWorkRamSize();
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} else if(_romInfo.IsInDatabase) {
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size = _romInfo.DatabaseInfo.WorkRamSize;
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} else {
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//Emulate as if a single 64k block of work/save ram existed (+ 1kb of ExRAM)
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size = (_romInfo.HasBattery ? 0 : 0x10000);
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}
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if(!HasBattery()) {
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size += MMC5::ExRamSize;
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}
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return size;
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}
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virtual bool AllowRegisterRead() override { return true; }
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virtual void InitMapper() override
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{
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AddRegisterRange(0xFFFA, 0xFFFB, MemoryOperation::Read);
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_audio.reset(new MMC5Audio(_console));
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//Override the 2000-2007 registers to catch all writes to the PPU registers (but not their mirrors)
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_mmc5MemoryHandler.reset(new MMC5MemoryHandler(_console.get()));
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_ppuIdleCounter = 0;
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_lastPpuReadAddr = 0;
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_ntReadCounter = 0;
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_prevChrA = false;
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_chrMode = 0;
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_prgRamProtect1 = 0;
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_prgRamProtect2 = 0;
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_extendedRamMode = 0;
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_nametableMapping = 0;
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_fillModeColor = 0;
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_fillModeTile = 0;
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_verticalSplitScroll = 0;
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_verticalSplitBank = 0;
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_verticalSplitEnabled = false;
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_verticalSplitDelimiterTile = 0;
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_verticalSplitRightSide = false;
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_multiplierValue1 = 0;
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_multiplierValue2 = 0;
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_chrUpperBits = 0;
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memset(_chrBanks, 0, sizeof(_chrBanks));
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_lastChrReg = 0;
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_exAttrLastFetchCounter = 0;
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_exAttributeLastNametableFetch = 0;
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_exAttrSelectedChrBank = 0;
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_irqPending = false;
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_irqCounterTarget = 0;
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_scanlineCounter = 0;
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_irqEnabled = false;
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_ppuInFrame = false;
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_needInFrame = false;
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_splitInSplitRegion = false;
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_splitVerticalScroll = 0;
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_splitTile = 0;
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_splitTileNumber = -1;
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memset(GetNametable(NtEmptyIndex), 0, BaseMapper::NametableSize);
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SetExtendedRamMode(0);
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//"Additionally, Romance of the 3 Kingdoms 2 seems to expect it to be in 8k PRG mode ($5100 = $03)."
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WriteRegister(0x5100, 0x03);
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//"Games seem to expect $5117 to be $FF on powerup (last PRG page swapped in)."
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WriteRegister(0x5117, 0xFF);
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UpdateChrBanks(true);
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}
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void Reset(bool softReset) override
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{
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_console->GetMemoryManager()->RegisterWriteHandler(_mmc5MemoryHandler.get(), 0x2000, 0x2007);
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}
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void StreamState(bool saving) override
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{
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BaseMapper::StreamState(saving);
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int16_t unusedPreviousScanline = 0;
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bool unusedSpriteFetch = false;
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bool unusedLargeSprites = false;
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ArrayInfo<uint8_t> prgBanks = { _prgBanks, 5 };
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ArrayInfo<uint16_t> chrBanks = { _chrBanks, 12 };
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SnapshotInfo audio{ _audio.get() };
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Stream(_prgRamProtect1, _prgRamProtect2, _fillModeTile, _fillModeColor, _verticalSplitEnabled, _verticalSplitRightSide,
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_verticalSplitDelimiterTile, _verticalSplitScroll, _verticalSplitBank, _multiplierValue1, _multiplierValue2,
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_nametableMapping, _extendedRamMode, _exAttributeLastNametableFetch, _exAttrLastFetchCounter, _exAttrSelectedChrBank,
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_prgMode, prgBanks, _chrMode, _chrUpperBits, chrBanks, _lastChrReg,
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unusedSpriteFetch, unusedLargeSprites, _irqCounterTarget, _irqEnabled, unusedPreviousScanline, _scanlineCounter, _irqPending, _ppuInFrame, audio,
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_splitInSplitRegion, _splitVerticalScroll, _splitTile, _splitTileNumber, _needInFrame);
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if(!saving) {
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UpdatePrgBanks();
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SetNametableMapping(_nametableMapping);
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}
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}
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virtual void WriteRAM(uint16_t addr, uint8_t value) override
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{
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if(addr >= 0x5C00 && addr <= 0x5FFF && _extendedRamMode <= 1 && !_ppuInFrame) {
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//Expansion RAM ($5C00-$5FFF, read/write)
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//Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
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value = 0;
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}
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BaseMapper::WriteRAM(addr, value);
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}
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void DetectScanlineStart(uint16_t addr)
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{
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if(addr >= 0x2000 && addr <= 0x2FFF) {
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if(_lastPpuReadAddr == addr) {
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//Count consecutive identical reads
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_ntReadCounter++;
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} else {
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_ntReadCounter = 0;
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}
|
|
|
|
if(_ntReadCounter >= 2) {
|
|
if(!_ppuInFrame && !_needInFrame) {
|
|
_needInFrame = true;
|
|
_scanlineCounter = 0;
|
|
} else {
|
|
_scanlineCounter++;
|
|
if(_irqCounterTarget == _scanlineCounter) {
|
|
_irqPending = true;
|
|
if(_irqEnabled) {
|
|
_console->GetCpu()->SetIrqSource(IRQSource::External);
|
|
}
|
|
}
|
|
}
|
|
_splitTileNumber = 0;
|
|
}
|
|
} else {
|
|
_ntReadCounter = 0;
|
|
}
|
|
}
|
|
|
|
virtual uint8_t MapperReadVRAM(uint16_t addr, MemoryOperationType memoryOperationType) override
|
|
{
|
|
bool isNtFetch = addr >= 0x2000 && addr <= 0x2FFF && (addr & 0x3FF) < 0x3C0;
|
|
if(isNtFetch) {
|
|
//Nametable data, not an attribute fetch
|
|
_splitInSplitRegion = false;
|
|
_splitTileNumber++;
|
|
|
|
if(_ppuInFrame) {
|
|
UpdateChrBanks(false);
|
|
} else if(_needInFrame) {
|
|
_needInFrame = false;
|
|
_ppuInFrame = true;
|
|
UpdateChrBanks(false);
|
|
}
|
|
}
|
|
DetectScanlineStart(addr);
|
|
|
|
_ppuIdleCounter = 3;
|
|
_lastPpuReadAddr = addr;
|
|
|
|
if(_extendedRamMode <= 1 && _ppuInFrame) {
|
|
if(_verticalSplitEnabled) {
|
|
uint16_t verticalSplitScroll = (_verticalSplitScroll + _scanlineCounter) % 240;
|
|
if(addr >= 0x2000) {
|
|
if(isNtFetch) {
|
|
uint8_t tileNumber = (_splitTileNumber + 2) % 42;
|
|
if(tileNumber <= 32 && ((_verticalSplitRightSide && tileNumber >= _verticalSplitDelimiterTile) || (!_verticalSplitRightSide && tileNumber < _verticalSplitDelimiterTile))) {
|
|
//Split region (for next 3 fetches, attribute + 2x tile data)
|
|
_splitInSplitRegion = true;
|
|
_splitTile = ((verticalSplitScroll & 0xF8) << 2) | tileNumber;
|
|
return InternalReadRam(0x5C00 + _splitTile);
|
|
} else {
|
|
//Outside of split region (or sprite data), result can get modified by ex ram mode code below
|
|
_splitInSplitRegion = false;
|
|
}
|
|
} else if(_splitInSplitRegion) {
|
|
return InternalReadRam(0x5FC0 | ((_splitTile & 0x380) >> 4) | ((_splitTile & 0x1F) >> 2));
|
|
}
|
|
} else if(_splitInSplitRegion) {
|
|
//CHR tile fetches for split region
|
|
return _chrRom[(_verticalSplitBank % (GetCHRPageCount() / 4)) * 0x1000 + (((addr & ~0x07) | (verticalSplitScroll & 0x07)) & 0xFFF)];
|
|
}
|
|
}
|
|
|
|
if(_extendedRamMode == 1 && (_splitTileNumber < 32 || _splitTileNumber >= 40)) {
|
|
//"In Mode 1, nametable fetches are processed normally, and can come from CIRAM nametables, fill mode, or even Expansion RAM, but attribute fetches are replaced by data from Expansion RAM."
|
|
//"Each byte of Expansion RAM is used to enhance the tile at the corresponding address in every nametable"
|
|
|
|
//When fetching NT data, we set a flag and then alter the VRAM values read by the PPU on the following 3 cycles (palette, tile low/high byte)
|
|
if(isNtFetch) {
|
|
//Nametable fetches
|
|
_exAttributeLastNametableFetch = addr & 0x03FF;
|
|
_exAttrLastFetchCounter = 3;
|
|
} else if(_exAttrLastFetchCounter > 0) {
|
|
//Attribute fetches
|
|
_exAttrLastFetchCounter--;
|
|
switch(_exAttrLastFetchCounter) {
|
|
case 2:
|
|
{
|
|
//PPU palette fetch
|
|
//Check work ram (expansion ram) to see which tile/palette to use
|
|
//Use InternalReadRam to bypass the fact that the ram is supposed to be write-only in mode 0/1
|
|
uint8_t value = InternalReadRam(0x5C00 + _exAttributeLastNametableFetch);
|
|
|
|
//"The pattern fetches ignore the standard CHR banking bits, and instead use the top two bits of $5130 and the bottom 6 bits from Expansion RAM to choose a 4KB bank to select the tile from."
|
|
_exAttrSelectedChrBank = ((value & 0x3F) | (_chrUpperBits << 6)) % (_chrRomSize / 0x1000);
|
|
|
|
//Return a byte containing the same palette 4 times - this allows the PPU to select the right palette no matter the shift value
|
|
uint8_t palette = (value & 0xC0) >> 6;
|
|
return palette | palette << 2 | palette << 4 | palette << 6;
|
|
}
|
|
|
|
case 1:
|
|
case 0:
|
|
//PPU tile data fetch (high byte & low byte)
|
|
return _chrRom[_exAttrSelectedChrBank * 0x1000 + (addr & 0xFFF)];
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return InternalReadVRAM(addr);
|
|
}
|
|
|
|
void WriteRegister(uint16_t addr, uint8_t value) override
|
|
{
|
|
if(addr >= 0x5113 && addr <= 0x5117) {
|
|
SwitchPrgBank(addr, value);
|
|
} else if(addr >= 0x5120 && addr <= 0x512B) {
|
|
SwitchChrBank(addr, value);
|
|
} else {
|
|
switch(addr) {
|
|
case 0x5000: case 0x5001: case 0x5002: case 0x5003: case 0x5004: case 0x5005: case 0x5006: case 0x5007: case 0x5010: case 0x5011: case 0x5015:
|
|
_audio->WriteRegister(addr, value);
|
|
break;
|
|
|
|
case 0x5100: _prgMode = value & 0x03; UpdatePrgBanks(); break;
|
|
case 0x5101: _chrMode = value & 0x03; UpdateChrBanks(true); break;
|
|
case 0x5102: _prgRamProtect1 = value & 0x03; UpdatePrgBanks(); break;
|
|
case 0x5103: _prgRamProtect2 = value & 0x03; UpdatePrgBanks(); break;
|
|
case 0x5104: SetExtendedRamMode(value & 0x03); break;
|
|
case 0x5105: SetNametableMapping(value); break;
|
|
case 0x5106: SetFillModeTile(value); break;
|
|
case 0x5107: SetFillModeColor(value & 0x03); break;
|
|
case 0x5130: _chrUpperBits = value & 0x03; break;
|
|
case 0x5200:
|
|
_verticalSplitEnabled = (value & 0x80) == 0x80;
|
|
_verticalSplitRightSide = (value & 0x40) == 0x40;
|
|
_verticalSplitDelimiterTile = (value & 0x1F);
|
|
break;
|
|
case 0x5201: _verticalSplitScroll = value; break;
|
|
case 0x5202: _verticalSplitBank = value; break;
|
|
case 0x5203: _irqCounterTarget = value; break;
|
|
case 0x5204:
|
|
_irqEnabled = (value & 0x80) == 0x80;
|
|
if(!_irqEnabled) {
|
|
_console->GetCpu()->ClearIrqSource(IRQSource::External);
|
|
} else if(_irqEnabled && _irqPending) {
|
|
_console->GetCpu()->SetIrqSource(IRQSource::External);
|
|
}
|
|
break;
|
|
case 0x5205: _multiplierValue1 = value; break;
|
|
case 0x5206: _multiplierValue2 = value; break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
uint8_t ReadRegister(uint16_t addr) override
|
|
{
|
|
switch(addr) {
|
|
case 0x5010: case 0x5015:
|
|
return _audio->ReadRegister(addr);
|
|
|
|
case 0x5204:
|
|
{
|
|
uint8_t value = (_ppuInFrame ? 0x40 : 0x00) | (_irqPending ? 0x80 : 0x00);
|
|
_irqPending = false;
|
|
_console->GetCpu()->ClearIrqSource(IRQSource::External);
|
|
return value;
|
|
}
|
|
|
|
case 0x5205: return (_multiplierValue1*_multiplierValue2) & 0xFF;
|
|
case 0x5206: return (_multiplierValue1*_multiplierValue2) >> 8;
|
|
|
|
case 0xFFFA:
|
|
case 0xFFFB:
|
|
_ppuInFrame = false;
|
|
UpdateChrBanks(true);
|
|
_lastPpuReadAddr = 0;
|
|
_scanlineCounter = 0;
|
|
_irqPending = false;
|
|
_console->GetCpu()->ClearIrqSource(IRQSource::External);
|
|
return DebugReadRAM(addr);
|
|
}
|
|
|
|
return _console->GetMemoryManager()->GetOpenBus();
|
|
}
|
|
|
|
public:
|
|
bool IsExtendedAttributes()
|
|
{
|
|
return _extendedRamMode == 1;
|
|
}
|
|
|
|
uint8_t GetExAttributeNtPalette(uint16_t ntAddr)
|
|
{
|
|
ntAddr &= 0x3FF;
|
|
uint8_t value = InternalReadRam(0x5C00 + ntAddr);
|
|
return (value & 0xC0) >> 6;
|
|
}
|
|
|
|
uint32_t GetExAttributeAbsoluteTileAddr(uint16_t ntAddr, uint16_t chrAddr)
|
|
{
|
|
ntAddr &= 0x3FF;
|
|
uint8_t value = InternalReadRam(0x5C00 + ntAddr);
|
|
|
|
//"The pattern fetches ignore the standard CHR banking bits, and instead use the top two bits of $5130 and the bottom 6 bits from Expansion RAM to choose a 4KB bank to select the tile from."
|
|
uint16_t chrBank = ((value & 0x3F) | (_chrUpperBits << 6)) % (_chrRomSize / 0x1000);
|
|
|
|
return chrBank * 0x1000 + (chrAddr & 0xFFF);
|
|
}
|
|
|
|
uint8_t GetExAttributeTileData(uint16_t ntAddr, uint16_t chrAddr)
|
|
{
|
|
return _chrRom[GetExAttributeAbsoluteTileAddr(ntAddr, chrAddr)];
|
|
}
|
|
};
|