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117 lines
3.1 KiB
C++
117 lines
3.1 KiB
C++
#pragma once
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#include "stdafx.h"
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#include "BaseMapper.h"
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class TaitoX1017 : public BaseMapper
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{
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private:
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uint8_t _chrMode;
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uint8_t _chrRegs[6];
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uint8_t _ramPermission[3];
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void UpdateRamAccess()
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{
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SetCpuMemoryMapping(0x6000, 0x63FF, 0, PrgMemoryType::SaveRam, _ramPermission[0] == 0xCA ? MemoryAccessType::ReadWrite : MemoryAccessType::NoAccess);
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SetCpuMemoryMapping(0x6400, 0x67FF, 1, PrgMemoryType::SaveRam, _ramPermission[0] == 0xCA ? MemoryAccessType::ReadWrite : MemoryAccessType::NoAccess);
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SetCpuMemoryMapping(0x6800, 0x6BFF, 2, PrgMemoryType::SaveRam, _ramPermission[1] == 0x69 ? MemoryAccessType::ReadWrite : MemoryAccessType::NoAccess);
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SetCpuMemoryMapping(0x6C00, 0x6FFF, 3, PrgMemoryType::SaveRam, _ramPermission[1] == 0x69 ? MemoryAccessType::ReadWrite : MemoryAccessType::NoAccess);
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SetCpuMemoryMapping(0x7000, 0x73FF, 4, PrgMemoryType::SaveRam, _ramPermission[2] == 0x84 ? MemoryAccessType::ReadWrite : MemoryAccessType::NoAccess);
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}
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protected:
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virtual uint16_t GetPRGPageSize() override { return 0x2000; }
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virtual uint16_t GetCHRPageSize() override { return 0x0400; }
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virtual uint16_t RegisterStartAddress() override { return 0x7EF0; }
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virtual uint16_t RegisterEndAddress() override { return 0x7EFF; }
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virtual uint32_t GetSaveRamSize() override { return 0x1400; }
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virtual uint32_t GetSaveRamPageSize() override { return 0x400; }
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void InitMapper() override
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{
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_chrMode = 0;
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memset(_ramPermission, 0, sizeof(_ramPermission));
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memset(_chrRegs, 0, sizeof(_chrRegs));
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SelectPRGPage(3, -1);
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UpdateRamAccess();
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}
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void UpdateChrBanking()
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{
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if(_chrMode == 0) {
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//Regs 0 & 1 ignore the LSB
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SelectChrPage2x(0, _chrRegs[0] & 0xFE);
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SelectChrPage2x(1, _chrRegs[1] & 0xFE);
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SelectCHRPage(4, _chrRegs[2]);
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SelectCHRPage(5, _chrRegs[3]);
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SelectCHRPage(6, _chrRegs[4]);
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SelectCHRPage(7, _chrRegs[5]);
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} else {
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SelectCHRPage(0, _chrRegs[2]);
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SelectCHRPage(1, _chrRegs[3]);
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SelectCHRPage(2, _chrRegs[4]);
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SelectCHRPage(3, _chrRegs[5]);
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//Regs 0 & 1 ignore the LSB
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SelectChrPage2x(2, _chrRegs[0] & 0xFE);
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SelectChrPage2x(3, _chrRegs[1] & 0xFE);
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}
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}
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void WriteRegister(uint16_t addr, uint8_t value) override
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{
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switch(addr) {
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case 0x7EF0:
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case 0x7EF1:
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case 0x7EF2:
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case 0x7EF3:
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case 0x7EF4:
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case 0x7EF5:
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_chrRegs[(addr & 0xF)] = value;
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UpdateChrBanking();
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break;
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case 0x7EF6:
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SetMirroringType((value & 0x01) == 0x01 ? MirroringType::Vertical : MirroringType::Horizontal);
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_chrMode = (value & 0x02) >> 1;
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UpdateChrBanking();
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break;
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case 0x7EF7:
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case 0x7EF8:
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case 0x7EF9:
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_ramPermission[(addr & 0xF) - 7] = value;
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UpdateRamAccess();
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break;
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case 0x7EFA:
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SelectPRGPage(0, value >> 2);
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break;
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case 0x7EFB:
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SelectPRGPage(1, value >> 2);
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break;
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case 0x7EFC:
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SelectPRGPage(2, value >> 2);
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break;
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}
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}
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virtual void StreamState(bool saving) override
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{
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BaseMapper::StreamState(saving);
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ArrayInfo<uint8_t> ramPermission = { _ramPermission, 3 };
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ArrayInfo<uint8_t> chrRegs = { _chrRegs, 6 };
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Stream(ramPermission, chrRegs, _chrMode);
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if(!saving) {
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UpdateRamAccess();
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}
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}
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}; |