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447 lines
14 KiB
C++
447 lines
14 KiB
C++
#pragma once
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#include "stdafx.h"
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#include "BaseMapper.h"
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#include "PPU.h"
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class MMC5 : public BaseMapper
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{
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private:
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const uint8_t NtWorkRamIndex = 4;
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const uint8_t NtEmptyIndex = 5;
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const uint8_t NtFillModeIndex = 6;
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uint8_t _prgRamProtect1;
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uint8_t _prgRamProtect2;
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uint8_t _fillModeTile;
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uint8_t _fillModeColor;
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uint8_t *_fillModeNametable;
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uint8_t *_emptyNametable;
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bool _verticalSplitEnabled;
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bool _verticalSplitRightSide;
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uint8_t _verticalSplitDelimiterTile;
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uint8_t _verticalSplitScroll;
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uint8_t _verticalSplitBank;
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uint8_t _multiplierValue1;
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uint8_t _multiplierValue2;
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uint8_t _nametableMapping;
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uint8_t _extendedRamMode;
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//Extended attribute mode fields (used when _extendedRamMode == 1)
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uint16_t _exAttributeLastNametableFetch;
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int8_t _exAttrLastFetchCounter;
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uint8_t _exAttrSelectedChrBank;
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uint8_t _prgMode;
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uint8_t _prgBanks[5];
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//CHR-related fields
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uint8_t _chrMode;
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uint8_t _chrUpperBits;
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uint16_t _chrBanks[12];
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uint16_t _lastChrReg;
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bool _spriteFetch;
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bool _largeSprites;
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//IRQ counter related fields
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uint8_t _irqCounterTarget;
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bool _irqEnabled;
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int16_t _previousScanline;
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uint8_t _irqCounter;
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bool _irqPending;
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bool _ppuInFrame;
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void SwitchPrgBank(uint16_t reg, uint8_t value)
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{
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_prgBanks[reg - 0x5113] = value;
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UpdatePrgBanks();
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}
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void GetCpuBankInfo(uint16_t reg, uint8_t &bankNumber, PrgMemoryType &memoryType, uint8_t &accessType)
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{
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bankNumber = _prgBanks[reg-0x5113];
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memoryType = PrgMemoryType::PrgRom;
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if((((bankNumber & 0x80) == 0x00) && reg != 0x04) || reg == 0x00) {
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bankNumber &= 0x07;
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memoryType = PrgMemoryType::SaveRam;
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accessType = MemoryAccessType::Read;
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if(_prgRamProtect1 == 0x02 && _prgRamProtect2 == 0x01) {
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accessType |= MemoryAccessType::Write;
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}
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} else {
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accessType = MemoryAccessType::Read;
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bankNumber &= 0x7F;
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}
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}
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void UpdatePrgBanks()
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{
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uint8_t value;
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PrgMemoryType memoryType;
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uint8_t accessType;
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GetCpuBankInfo(0x5113, value, memoryType, accessType);
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SetCpuMemoryMapping(0x6000, 0x7FFF, value, memoryType, accessType);
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//PRG Bank 0
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//Mode 0,1,2 - Ignored
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//Mode 3 - Select an 8KB PRG bank at $8000-$9FFF
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if(_prgMode == 3) {
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GetCpuBankInfo(0x5114, value, memoryType, accessType);
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SetCpuMemoryMapping(0x8000, 0x9FFF, value, memoryType, accessType);
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}
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//PRG Bank 1
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//Mode 0 - Ignored
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//Mode 1,2 - Select a 16KB PRG bank at $8000-$BFFF (ignore bottom bit)
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//Mode 3 - Select an 8KB PRG bank at $A000-$BFFF
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GetCpuBankInfo(0x5115, value, memoryType, accessType);
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if(_prgMode == 1 || _prgMode == 2) {
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SetCpuMemoryMapping(0x8000, 0xBFFF, value & 0xFE, memoryType, accessType);
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} else if(_prgMode == 3) {
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SetCpuMemoryMapping(0xA000, 0xBFFF, value, memoryType, accessType);
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}
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//Mode 0,1 - Ignored
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//Mode 2,3 - Select an 8KB PRG bank at $C000-$DFFF
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if(_prgMode == 2 || _prgMode == 3) {
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GetCpuBankInfo(0x5116, value, memoryType, accessType);
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SetCpuMemoryMapping(0xC000, 0xDFFF, value, memoryType, accessType);
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}
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//Mode 0 - Select a 32KB PRG ROM bank at $8000-$FFFF (ignore bottom 2 bits)
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//Mode 1 - Select a 16KB PRG ROM bank at $C000-$FFFF (ignore bottom bit)
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//Mode 2,3 - Select an 8KB PRG ROM bank at $E000-$FFFF
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GetCpuBankInfo(0x5117, value, memoryType, accessType);
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if(_prgMode == 0) {
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SetCpuMemoryMapping(0x8000, 0xFFFF, value & 0x7C, memoryType, accessType);
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} else if(_prgMode == 1) {
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SetCpuMemoryMapping(0xC000, 0xFFFF, value & 0x7E, memoryType, accessType);
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} else if(_prgMode == 2 || _prgMode == 3) {
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SetCpuMemoryMapping(0xE000, 0xFFFF, value & 0x7F, memoryType, accessType);
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}
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}
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void SwitchChrBank(uint16_t reg, uint8_t value)
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{
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_chrBanks[reg - 0x5120] = value | (_chrUpperBits << 8);
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_lastChrReg = reg;
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UpdateChrBanks(!PPU::GetControlFlags().BackgroundEnabled && !PPU::GetControlFlags().SpritesEnabled);
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}
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void UpdateChrBanks(bool forceA = false)
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{
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_spriteFetch = IsSpriteFetch();
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_largeSprites = PPU::GetControlFlags().LargeSprites;
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bool chrA = forceA || (_largeSprites && _spriteFetch) || (!_largeSprites && _lastChrReg <= 0x5127);
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if(_chrMode == 0) {
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SelectChrPage8x(0, _chrBanks[chrA ? 0x07 : 0x0B] << 3);
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} else if(_chrMode == 1) {
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SelectChrPage4x(0, _chrBanks[chrA ? 0x03 : 0x0B] << 2);
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SelectChrPage4x(1, _chrBanks[chrA ? 0x07 : 0x0B] << 2);
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} else if(_chrMode == 2) {
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SelectChrPage2x(0, _chrBanks[chrA ? 0x01 : 0x09] << 1);
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SelectChrPage2x(1, _chrBanks[chrA ? 0x03 : 0x0B] << 1);
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SelectChrPage2x(2, _chrBanks[chrA ? 0x05 : 0x09] << 1);
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SelectChrPage2x(3, _chrBanks[chrA ? 0x07 : 0x0B] << 1);
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} else if(_chrMode == 3) {
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SelectCHRPage(0, _chrBanks[chrA ? 0x00 : 0x08]);
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SelectCHRPage(1, _chrBanks[chrA ? 0x01 : 0x09]);
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SelectCHRPage(2, _chrBanks[chrA ? 0x02 : 0x0A]);
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SelectCHRPage(3, _chrBanks[chrA ? 0x03 : 0x0B]);
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SelectCHRPage(4, _chrBanks[chrA ? 0x04 : 0x08]);
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SelectCHRPage(5, _chrBanks[chrA ? 0x05 : 0x09]);
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SelectCHRPage(6, _chrBanks[chrA ? 0x06 : 0x0A]);
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SelectCHRPage(7, _chrBanks[chrA ? 0x07 : 0x0B]);
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}
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}
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void ProcessCpuClock()
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{
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if(!PPU::GetControlFlags().BackgroundEnabled && !PPU::GetControlFlags().SpritesEnabled) {
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_ppuInFrame = false;
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}
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}
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virtual void NotifyVRAMAddressChange(uint16_t addr)
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{
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if(_spriteFetch != IsSpriteFetch() || _largeSprites != PPU::GetControlFlags().LargeSprites) {
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if(PPU::GetControlFlags().BackgroundEnabled || PPU::GetControlFlags().SpritesEnabled) {
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UpdateChrBanks();
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}
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}
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int16_t currentScanline = PPU::GetCurrentScanline();
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if(currentScanline != _previousScanline) {
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if(currentScanline >= 239 || currentScanline < 0) {
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_ppuInFrame = false;
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} else {
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if(!_ppuInFrame) {
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_ppuInFrame = true;
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_irqCounter = 0;
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_irqPending = false;
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CPU::ClearIRQSource(IRQSource::External);
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} else {
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_irqCounter++;
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if(_irqCounter == _irqCounterTarget) {
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_irqPending = true;
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if(_irqEnabled) {
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CPU::SetIRQSource(IRQSource::External);
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}
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}
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}
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}
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_previousScanline = currentScanline;
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}
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}
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void SetNametableMapping(uint8_t value)
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{
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_nametableMapping = value;
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uint8_t nametables[4] = {
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0, //"0 - On-board VRAM page 0"
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1, //"1 - On-board VRAM page 1"
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_extendedRamMode <= 1 ? NtWorkRamIndex : NtEmptyIndex, //"2 - Internal Expansion RAM, only if the Extended RAM mode allows it ($5104 is 00/01); otherwise, the nametable will read as all zeros,"
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NtFillModeIndex //"3 - Fill-mode data"
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};
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SetNametables(nametables[value & 0x03], nametables[(value >> 2) & 0x03], nametables[(value >> 4) & 0x03], nametables[(value >> 6) & 0x03]);
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}
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void SetExtendedRamMode(uint8_t mode)
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{
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_extendedRamMode = mode;
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if(_extendedRamMode <= 1) {
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//"Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)"
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//See overridden WriteRam function for implementation
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SetCpuMemoryMapping(0x5C00, 0x5FFF, 0, PrgMemoryType::WorkRam, MemoryAccessType::Write);
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} else if(_extendedRamMode == 2) {
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//"Mode 2 - Readable and writable"
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SetCpuMemoryMapping(0x5C00, 0x5FFF, 0, PrgMemoryType::WorkRam, MemoryAccessType::ReadWrite);
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} else {
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//"Mode 3 - Read-only"
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SetCpuMemoryMapping(0x5C00, 0x5FFF, 0, PrgMemoryType::WorkRam, MemoryAccessType::Read);
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}
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SetNametableMapping(_nametableMapping);
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}
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void SetFillModeTile(uint8_t tile)
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{
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_fillModeTile = tile;
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memset(_fillModeNametable, tile, 32 * 30); //32 tiles per row, 30 rows
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}
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void SetFillModeColor(uint8_t color)
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{
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_fillModeColor = color;
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memset(_fillModeNametable + 32 * 30, color, 64); //Attribute table is 64 bytes
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}
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bool IsSpriteFetch()
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{
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return PPU::GetCurrentCycle() >= 257 && PPU::GetCurrentCycle() < 321;
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}
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protected:
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virtual uint16_t GetPRGPageSize() { return 0x2000; }
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virtual uint16_t GetCHRPageSize() { return 0x400; }
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virtual uint16_t RegisterStartAddress() { return 0x5000; }
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virtual uint16_t RegisterEndAddress() { return 0x5206; }
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virtual uint32_t GetSaveRamSize() { return 0x10000; } //Emulate as if a single 64k block of saved ram existed
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virtual uint32_t GetSaveRamPageSize() { return 0x2000; }
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virtual uint32_t GetWorkRamSize() { return 0x400; }
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virtual uint32_t GetWorkRamPageSize() { return 0x400; }
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virtual bool AllowRegisterRead() { return true; }
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virtual void InitMapper()
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{
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_hasBattery = true;
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_chrMode = 0;
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_prgRamProtect1 = 0;
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_prgRamProtect2 = 0;
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_extendedRamMode = 0;
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_fillModeColor = 0;
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_fillModeTile = 0;
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_verticalSplitScroll = 0;
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_verticalSplitBank = 0;
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_multiplierValue1 = 0;
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_multiplierValue2 = 0;
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_chrUpperBits = 0;
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memset(_chrBanks, 0, sizeof(_chrBanks));
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_lastChrReg = 0;
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_spriteFetch = false;
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_largeSprites = false;
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_exAttrLastFetchCounter = 0;
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_exAttributeLastNametableFetch = 0;
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_exAttrSelectedChrBank = 0;
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_irqCounterTarget = 0;
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_irqCounter = 0;
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_irqEnabled = false;
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_previousScanline = -1;
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_ppuInFrame = false;
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_fillModeNametable = new uint8_t[0x400];
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_emptyNametable = new uint8_t[0x400];
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memset(_emptyNametable, 0, 0x400);
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//"Expansion RAM ($5C00-$5FFF, read/write)"
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SetCpuMemoryMapping(0x5C00, 0x5FFF, 0, PrgMemoryType::WorkRam);
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AddNametable(NtWorkRamIndex, _workRam);
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AddNametable(NtEmptyIndex, _emptyNametable);
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AddNametable(NtFillModeIndex, _fillModeNametable);
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//"Additionally, Romance of the 3 Kingdoms 2 seems to expect it to be in 8k PRG mode ($5100 = $03)."
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WriteRegister(0x5100, 0x03);
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//"Games seem to expect $5117 to be $FF on powerup (last PRG page swapped in)."
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WriteRegister(0x5117, 0xFF);
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}
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virtual ~MMC5()
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{
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delete[] _fillModeNametable;
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delete[] _emptyNametable;
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}
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void StreamState(bool saving)
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{
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BaseMapper::StreamState(saving);
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ArrayInfo<uint8_t> prgBanks = { _prgBanks, 5 };
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ArrayInfo<uint16_t> chrBanks = { _chrBanks, 12 };
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Stream(_prgRamProtect1, _prgRamProtect2, _fillModeTile, _fillModeColor, _verticalSplitEnabled, _verticalSplitRightSide,
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_verticalSplitDelimiterTile, _verticalSplitScroll, _verticalSplitBank, _multiplierValue1, _multiplierValue2,
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_nametableMapping, _extendedRamMode, _exAttributeLastNametableFetch, _exAttrLastFetchCounter, _exAttrSelectedChrBank,
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_prgMode, prgBanks, _chrMode, _chrUpperBits, chrBanks, _lastChrReg,
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_spriteFetch, _largeSprites, _irqCounterTarget, _irqEnabled, _previousScanline, _irqCounter, _irqPending, _ppuInFrame);
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if(!saving) {
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UpdatePrgBanks();
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}
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}
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virtual void WriteRAM(uint16_t addr, uint8_t value)
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{
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if(addr >= 0x5C00 && addr <= 0x5FFF && _extendedRamMode <= 1) {
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PPUControlFlags flags = PPU::GetControlFlags();
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if(!flags.BackgroundEnabled && !flags.SpritesEnabled) {
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//Expansion RAM ($5C00-$5FFF, read/write)
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//Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
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value = 0;
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}
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}
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BaseMapper::WriteRAM(addr, value);
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}
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virtual uint8_t ReadVRAM(uint16_t addr)
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{
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if(_extendedRamMode == 1) {
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//"In Mode 1, nametable fetches are processed normally, and can come from CIRAM nametables, fill mode, or even Expansion RAM, but attribute fetches are replaced by data from Expansion RAM."
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//"Each byte of Expansion RAM is used to enhance the tile at the corresponding address in every nametable"
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//When fetching NT data, we set a flag and then alter the VRAM values read by the PPU on the following 3 cycles (palette, tile low/high byte)
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if(addr >= 0x2000 && (addr & 0x3FF) < 0x3C0) {
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//Nametable fetches
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_exAttributeLastNametableFetch = addr & 0x03FF;
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_exAttrLastFetchCounter = 3;
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} else if(_exAttrLastFetchCounter > 0) {
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//Attribute fetches
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_exAttrLastFetchCounter--;
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switch(_exAttrLastFetchCounter) {
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case 2:
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{
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//PPU palette fetch
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//Check work ram (expansion ram) to see which tile/palette to use
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//Use InternalReadRam to bypass the fact that the ram is supposed to be write-only in mode 0/1
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uint8_t value = InternalReadRam(0x5C00 + _exAttributeLastNametableFetch);
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//"The pattern fetches ignore the standard CHR banking bits, and instead use the top two bits of $5130 and the bottom 6 bits from Expansion RAM to choose a 4KB bank to select the tile from."
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_exAttrSelectedChrBank = ((value & 0x3F) | (_chrUpperBits << 6)) % (_chrRomSize / 0x1000);
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//Return a byte containing the same palette 4 times - this allows the PPU to select the right palette no matter the shift value
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uint8_t palette = (value & 0xC0) >> 6;
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return palette | palette << 2 | palette << 4 | palette << 6;
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}
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case 1:
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case 0:
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//PPU tile data fetch (high byte & low byte)
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return _chrRom[_exAttrSelectedChrBank * 0x1000 + (addr & 0xFFF)];
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}
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}
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}
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return BaseMapper::ReadVRAM(addr);
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}
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void WriteRegister(uint16_t addr, uint8_t value)
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{
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if(addr >= 0x5113 && addr <= 0x5117) {
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SwitchPrgBank(addr, value);
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} else if(addr >= 0x5120 && addr <= 0x512B) {
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SwitchChrBank(addr, value);
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} else {
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switch(addr) {
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case 0x5100: _prgMode = value & 0x03; UpdatePrgBanks(); break;
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case 0x5101: _chrMode = value & 0x03; UpdateChrBanks(); break;
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case 0x5102: _prgRamProtect1 = value & 0x03; UpdatePrgBanks(); break;
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case 0x5103: _prgRamProtect2 = value & 0x03; UpdatePrgBanks(); break;
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case 0x5104: SetExtendedRamMode(value & 0x03); break;
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case 0x5105: SetNametableMapping(value); break;
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case 0x5106: SetFillModeTile(value); break;
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case 0x5107: SetFillModeColor(value & 0x03); break;
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case 0x5130: _chrUpperBits = value & 0x03; break;
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case 0x5200:
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_verticalSplitEnabled = (value & 0x80) == 0x80;
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_verticalSplitRightSide = (value & 0x40) == 0x40;
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_verticalSplitDelimiterTile = (value & 0x1F);
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break;
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case 0x5201: _verticalSplitScroll = value; break;
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case 0x5202: _verticalSplitBank = value; break;
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case 0x5203: _irqCounterTarget = value; break;
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case 0x5204:
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_irqEnabled = (value & 0x80) == 0x80;
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if(!_irqEnabled) {
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CPU::ClearIRQSource(IRQSource::External);
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} else if(_irqEnabled && _irqPending) {
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CPU::SetIRQSource(IRQSource::External);
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}
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break;
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case 0x5205: _multiplierValue1 = value; break;
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case 0x5206: _multiplierValue2 = value; break;
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default:
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break;
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}
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}
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}
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uint8_t ReadRegister(uint16_t addr)
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{
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switch(addr) {
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case 0x5204:
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{
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uint8_t value = (_ppuInFrame ? 0x40 : 0x00) | (_irqPending ? 0x80 : 0x00);
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_irqPending = false;
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CPU::ClearIRQSource(IRQSource::External);
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return value;
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}
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case 0x5205: return (_multiplierValue1*_multiplierValue2) & 0xFF;
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case 0x5206: return (_multiplierValue1*_multiplierValue2) >> 8;
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}
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return 0;
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|
}
|
|
};
|