mirror of
https://github.com/daeken/SteelBreeze.git
synced 2024-05-16 03:40:29 -04:00
Committed new interpreter gen.
This commit is contained in:
Cody Brocious
parent
be4fdedaa1
commit
5c3ba53a4c
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@ -1,2 +1,8 @@
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#include <stdio.h>
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#include <stdlib.h>
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#define null NULL
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#define WARN(msg) { printf("%s\n", msg); }
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#define ASSERT(comp, msg) { if(!(comp)) { printf("%s\n", msg); exit(1); } }
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#define BAIL(msg) { printf("%s\n", msg); exit(1); }
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@ -1,18 +1,20 @@
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#include <stdint.h>
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#define EMU_ADDR(off) (void *) (((uint8_t *) MemoryBase) + (off))
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class CPU {
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public:
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CPU(void *base) : MemoryBase(base),
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Eip(0),
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Eax(0), Ebx(0), Ecx(0), Edx(0),
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Ebp(0), Esp(0), Ebi(0), Edi(0) {}
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Ebp(0), Esp(0), Edi(0), Esi(0) {}
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virtual ~CPU() {}
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virtual void Run() {}
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uint32_t Eax, Ebx, Ecx, Edx,
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Ebp, Esp, Ebi, Edi;
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Ebp, Esp, Edi, Esi;
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uint32_t Eip;
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void *MemoryBase;
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90
Core/CPU/Interpreter/Instructions.hpp
Normal file
90
Core/CPU/Interpreter/Instructions.hpp
Normal file
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@ -0,0 +1,90 @@
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#define INSN_ADD(a, b) { a = a + b; }
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#define INSN_JMP(a) { eip += a; }
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#define INSN_AAA() { WARN("STUB Instruction AAA"); }
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#define INSN_AAD(a) { WARN("STUB Instruction AAD"); }
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#define INSN_AAM(a) { WARN("STUB Instruction AAM"); }
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#define INSN_AAS() { WARN("STUB Instruction AAS"); }
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#define INSN_ADC(a, b) { WARN("STUB Instruction ADC"); }
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#define INSN_AND(a, b) { WARN("STUB Instruction AND"); }
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#define INSN_ARPL(a, b) { WARN("STUB Instruction ARPL"); }
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#define INSN_BOUND(a, b) { WARN("STUB Instruction BOUND"); }
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#define INSN_CALL(a) { WARN("STUB Instruction CALL"); }
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#define INSN_CDQ() { WARN("STUB Instruction CDQ"); }
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#define INSN_CLC() { WARN("STUB Instruction CLC"); }
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#define INSN_CLD() { WARN("STUB Instruction CLD"); }
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#define INSN_CLI() { WARN("STUB Instruction CLI"); }
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#define INSN_CMC() { WARN("STUB Instruction CMC"); }
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#define INSN_CMP(a, b) { WARN("STUB Instruction CMP"); }
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#define INSN_CMPS(a, b) { WARN("STUB Instruction CMPS"); }
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#define INSN_CWDE() { WARN("STUB Instruction CWDE"); }
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#define INSN_DAA() { WARN("STUB Instruction DAA"); }
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#define INSN_DAS() { WARN("STUB Instruction DAS"); }
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#define INSN_DEC(a) { WARN("STUB Instruction DEC"); }
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#define INSN_ENTER(a, b) { WARN("STUB Instruction ENTER"); }
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#define INSN_HLT() { WARN("STUB Instruction HLT"); }
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#define INSN_IMUL(a, b, c) { WARN("STUB Instruction IMUL"); }
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#define INSN_IN(a, b) { WARN("STUB Instruction IN"); }
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#define INSN_INC(a) { WARN("STUB Instruction INC"); }
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#define INSN_INS(a, b) { WARN("STUB Instruction INS"); }
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#define INSN_INT(a) { WARN("STUB Instruction INT"); }
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#define INSN_INT1() { WARN("STUB Instruction INT1"); }
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#define INSN_INT3() { WARN("STUB Instruction INT3"); }
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#define INSN_INTO() { WARN("STUB Instruction INTO"); }
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#define INSN_IRET() { WARN("STUB Instruction IRET"); }
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#define INSN_JB(a) { WARN("STUB Instruction JB"); }
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#define INSN_JBE(a) { WARN("STUB Instruction JBE"); }
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#define INSN_JCXZ(a) { WARN("STUB Instruction JCXZ"); }
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#define INSN_JL(a) { WARN("STUB Instruction JL"); }
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#define INSN_JLE(a) { WARN("STUB Instruction JLE"); }
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#define INSN_JNB(a) { WARN("STUB Instruction JNB"); }
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#define INSN_JNBE(a) { WARN("STUB Instruction JNBE"); }
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#define INSN_JNL(a) { WARN("STUB Instruction JNL"); }
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#define INSN_JNLE(a) { WARN("STUB Instruction JNLE"); }
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#define INSN_JNO(a) { WARN("STUB Instruction JNO"); }
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#define INSN_JNP(a) { WARN("STUB Instruction JNP"); }
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#define INSN_JNS(a) { WARN("STUB Instruction JNS"); }
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#define INSN_JNZ(a) { WARN("STUB Instruction JNZ"); }
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#define INSN_JO(a) { WARN("STUB Instruction JO"); }
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#define INSN_JP(a) { WARN("STUB Instruction JP"); }
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#define INSN_JS(a) { WARN("STUB Instruction JS"); }
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#define INSN_JZ(a) { WARN("STUB Instruction JZ"); }
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#define INSN_LAHF() { WARN("STUB Instruction LAHF"); }
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#define INSN_LDS(a, b) { WARN("STUB Instruction LDS"); }
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#define INSN_LEA(a, b) { WARN("STUB Instruction LEA"); }
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#define INSN_LEAVE() { WARN("STUB Instruction LEAVE"); }
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#define INSN_LES(a, b) { WARN("STUB Instruction LES"); }
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#define INSN_LODS(a, b) { WARN("STUB Instruction LODS"); }
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#define INSN_LOOP(a) { WARN("STUB Instruction LOOP"); }
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#define INSN_LOOPNZ(a) { WARN("STUB Instruction LOOPNZ"); }
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#define INSN_LOOPZ(a) { WARN("STUB Instruction LOOPZ"); }
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#define INSN_MOV(a, b) { WARN("STUB Instruction MOV"); }
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#define INSN_MOVS(a, b) { WARN("STUB Instruction MOVS"); }
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#define INSN_NOP() { WARN("STUB Instruction NOP"); }
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#define INSN_OR(a, b) { WARN("STUB Instruction OR"); }
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#define INSN_OUT(a, b) { WARN("STUB Instruction OUT"); }
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#define INSN_OUTS(a, b) { WARN("STUB Instruction OUTS"); }
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#define INSN_POP(a) { WARN("STUB Instruction POP"); }
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#define INSN_POPA() { WARN("STUB Instruction POPA"); }
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#define INSN_POPF() { WARN("STUB Instruction POPF"); }
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#define INSN_PUSH(a) { WARN("STUB Instruction PUSH"); }
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#define INSN_PUSHA() { WARN("STUB Instruction PUSHA"); }
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#define INSN_PUSHF() { WARN("STUB Instruction PUSHF"); }
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#define INSN_RETfar_off(a) { WARN("STUB Instruction RETfar_off"); }
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#define INSN_RETfar() { WARN("STUB Instruction RETfar"); }
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#define INSN_RETnear_off(a) { WARN("STUB Instruction RETnear_off"); }
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#define INSN_RETnear() { WARN("STUB Instruction RETnear"); }
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#define INSN_SAHF() { WARN("STUB Instruction SAHF"); }
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#define INSN_SALC() { WARN("STUB Instruction SALC"); }
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#define INSN_SBB(a, b) { WARN("STUB Instruction SBB"); }
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#define INSN_SCAS(a, b) { WARN("STUB Instruction SCAS"); }
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#define INSN_STC() { WARN("STUB Instruction STC"); }
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#define INSN_STD() { WARN("STUB Instruction STD"); }
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#define INSN_STI() { WARN("STUB Instruction STI"); }
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#define INSN_STOS(a, b) { WARN("STUB Instruction STOS"); }
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#define INSN_SUB(a, b) { WARN("STUB Instruction SUB"); }
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#define INSN_TEST(a, b) { WARN("STUB Instruction TEST"); }
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#define INSN_WAIT() { WARN("STUB Instruction WAIT"); }
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#define INSN_XCHG(a, b) { WARN("STUB Instruction XCHG"); }
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#define INSN_XLAT() { WARN("STUB Instruction XLAT"); }
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#define INSN_XOR(a, b) { WARN("STUB Instruction XOR"); }
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@ -1,4 +1,5 @@
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#include "Interpreter.hpp"
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#include "Instructions.hpp"
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void Interpreter::Run() {
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while(true) {
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@ -25,25 +26,10 @@ void Interpreter::Run() {
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uint8_t op = *eip++;
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Eip++;
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printf("Op %02x\n", op);
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printf("Eax %08x\n", Eax);
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// Instructions
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switch(op) {
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case 0x05: {// ADD rAX, Iz
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int32_t val;
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if(opsize) { // 16-bit
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val = *(int16_t *) eip;
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eip += 2;
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} else {
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val = *(int32_t *) eip;
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eip += 4;
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}
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Eax += val;
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printf("%08x\n", Eax);
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break;
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}
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case 0xEB: {// JMP Ib
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eip += (int8_t) *eip++;
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break;
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}
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#include "Interpreter_inst.cgen"
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default: {
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printf("Undefined opcode %02x @ %08X\n", op, Eip);
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exit(1);
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@ -52,3 +38,32 @@ void Interpreter::Run() {
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Eip = (uint32_t) (eip - (uint8_t *) MemoryBase);
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}
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}
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void *Interpreter::RmAddr(uint8_t mod, uint8_t rm, int size) {
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return null;
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}
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void *Interpreter::Reg(int reg, int size) {
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uint32_t *regaddr;
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size_t off = 0;
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if(reg > 4 && size == 1) {
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reg -= 4;
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off = 1;
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}
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switch(reg) {
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case 0: regaddr = &Eax; break;
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case 1: regaddr = &Ecx; break;
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case 2: regaddr = &Edx; break;
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case 3: regaddr = &Ebx; break;
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case 4: regaddr = &Esp; break;
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case 5: regaddr = &Ebp; break;
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case 6: regaddr = &Esi; break;
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case 7: regaddr = &Edi; break;
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}
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return ((uint8_t *) regaddr) + off;
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}
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uint16_t *Interpreter::SegReg(int reg) {
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return null;
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}
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Interpreter(void *base) : CPU(base) {
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}
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void Run();
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void *RmAddr(uint8_t mod, uint8_t rm, int size);
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void *Reg(int reg, int size);
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uint16_t *SegReg(int reg);
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};
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@ -3,7 +3,7 @@
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int main(void) {
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uint8_t memory[11];
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memory[0] = 0x05; *((uint32_t *) (memory+1)) = 0x00000001;
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memory[5] = 0x66; memory[6] = 0x05; *((uint32_t *) (memory+7)) = 0x00000002;
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memory[5] = 0x66; memory[6] = 0x05; *((uint16_t *) (memory+7)) = 0x0007;
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memory[9] = 0xEB; memory[10] = 0xF5;
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Interpreter interpreter((void *) memory);
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interpreter.Run();
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167
Core/Generators/InterpreterGen.py
Normal file
167
Core/Generators/InterpreterGen.py
Normal file
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@ -0,0 +1,167 @@
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from opcodes import opcodes
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import sys
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onebyte = sorted([opcd for opcd in opcodes.keys() if not isinstance(opcd, tuple)])
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fp = file('Core/CPU/Interpreter/Interpreter_inst.cgen', 'w')
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registers = {}
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for i, reg in enumerate('AL CL DL BL AH CH DH BH'.split(' ')):
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registers[reg] = i, 1
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for i, reg in enumerate('AX CX DX BX SP BP SI DI'.split(' ')):
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registers[reg] = i, 2
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for i, reg in enumerate('EAX ECX EDX EBX ESP EBP ESI EDI'.split(' ')):
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registers[reg] = i, 4
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registers[reg.replace('E', 'R')] = i, 4
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segmentRegisters = dict(CS=0, DS=1, SS=2, ES=3, FS=4, GS=5)
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size2type = {1: 'uint8_t', 2: 'uint16_t', 4: 'uint32_t'}
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for opcd in onebyte:
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insn, operands = opcodes[opcd]
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print >>fp, 'case 0x%02X: { // %s' % (opcd, '%s %s' % (insn, ','.join(operands)))
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hasModrm = False
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opsizeDependent = False
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for operand in operands:
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if operand[0] in 'MGERPQNVWU' and (len(operand) == 1 or operand[1] not in 'S'):
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hasModrm = True
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if len(operand) > 1 and operand[1] in 'vz':
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opsizeDependent = True
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if hasModrm:
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print >>fp, '\tuint8_t mod = *eip >> 6, reg = (*eip >> 3) & 0x7, rm = *eip & 0x7;'
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print >>fp, '\teip++;'
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def generateSet(opsize):
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def addr(type, expr):
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print >>fp, '\t\t%s *_%i = (%s *) %s;' % (type, i, type, expr)
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params.append('(*_%i)' % i)
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def value(type, expr):
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print >>fp, '\t\t%s _%i = (%s) %s;' % (type, i, type, expr)
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params.append('_%i' % i)
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params = []
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for i, operand in enumerate(operands):
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if len(operand) == 2:
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a, b = list(operand)
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if opsizeDependent and b in 'vz':
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b = 'w' if opsize else 'd'
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else:
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a = b = None
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if operand.upper() in registers:
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reg, size = registers[operand.upper()]
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addr(size2type[size], 'Reg(%i, %i)' % (reg, size))
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elif operand in segmentRegisters:
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reg = segmentRegisters[operand]
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addr('int16_t', 'SegReg(%i)' % (reg))
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elif a == 'E':
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if b == 'b':
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addr('int8_t', 'RmAddr(mod, rm, 1)')
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elif b == 'w':
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addr('int16_t', 'RmAddr(mod, rm, 2)')
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elif b == 'd':
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addr('int32_t', 'RmAddr(mod, rm, 4)')
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else:
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assert False
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elif a == 'G':
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if b == 'b':
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addr('int8_t', 'Reg(reg, 1)')
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elif b == 'w':
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addr('int16_t', 'Reg(reg, 2)')
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elif b == 'd':
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addr('int32_t', 'Reg(reg, 4)')
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else:
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assert False
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elif a in 'IJ':
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if b == 'b':
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value('int8_t', '*eip++')
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elif b == 'w':
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value('int16_t', '*(int16_t *) eip')
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print >>fp, '\t\teip += 2;'
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elif b == 'd':
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value('int32_t', '*(int32_t *) eip')
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print >>fp, '\t\teip += 4;'
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else:
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assert False
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elif a == 'M':
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if b == 'a':
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print >>fp, '\t\tASSERT(mod != 11, "M instructions require memory operands");'
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if opsize:
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addr('int16_t', 'RmAddr(mod, rm, 2)')
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else:
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addr('int32_t', 'RmAddr(mod, rm, 4)')
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elif b == 'p':
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print >>fp, '\t\tBAIL("Mp instructions unsupported.");'
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addr('void', '0')
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else:
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assert False
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elif a == 'X':
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if b == 'b':
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addr('int8_t', 'EMU_ADDR(Esi)')
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elif b == 'w':
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addr('int16_t', 'EMU_ADDR(Esi)')
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elif b == 'd':
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addr('int32_t', 'EMU_ADDR(Esi)')
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else:
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assert False
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elif a == 'Y':
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print >>fp, '\t\tWARN("Y operands use data segment.");'
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if b == 'b':
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addr('int8_t', 'EMU_ADDR(Edi)')
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elif b == 'w':
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addr('int16_t', 'EMU_ADDR(Edi)')
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elif b == 'd':
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addr('int32_t', 'EMU_ADDR(Edi)')
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else:
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assert False
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elif a == 'A':
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print >>fp, '\t\tWARN("Address and no ADSIZE: support.");'
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if b == 'p':
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addr('int32_t', 'eip')
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print >>fp, '\t\teip += 32;'
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else:
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assert False
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elif a == 'O':
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print >>fp, '\t\tWARN("Address and no ADSIZE: support.");'
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if b == 'b':
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addr('int8_t', 'EMU_ADDR(*(int32_t *) eip)')
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print >>fp, '\t\teip += 4;'
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elif b == 'w':
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addr('int16_t', 'EMU_ADDR(*(int32_t *) eip)')
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print >>fp, '\t\teip += 4;'
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elif b == 'd':
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addr('int32_t', 'EMU_ADDR(*(int32_t *) eip)')
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print >>fp, '\t\teip += 4;'
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else:
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assert False
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else:
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assert False
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print >>fp, '\t\tINSN_%s(%s)' % (insn, ', '.join(params))
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if opsizeDependent:
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print >>fp, '\tif(opsize) {'
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generateSet(True)
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print >>fp, '\t} else {'
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generateSet(False)
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print >>fp, '\t}'
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else:
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print >>fp, '\t{'
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generateSet(False)
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print >>fp, '\t}'
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print >>fp, '\tbreak;'
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print >>fp, '}'
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stubs = []
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for insn, operands in opcodes.values():
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paramcount = len(operands)
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if (insn, paramcount) not in stubs:
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stubs.append((insn, paramcount))
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stubs = sorted(stubs, key=lambda x: x[0])
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for insn, paramcount in stubs:
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print '#define INSN_%s(%s) { WARN("STUB Instruction %s"); }' % (insn, ', '.join(chr(ord('a') + i) for i in xrange(paramcount)), insn)
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23
Core/Generators/opcodes.py
Normal file
23
Core/Generators/opcodes.py
Normal file
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@ -0,0 +1,23 @@
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opcodes = {}
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fp = file('Core/Generators/opcodes.txt')
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||||
|
||||
for line in fp:
|
||||
line = line.strip()
|
||||
try:
|
||||
hex, insn, operands = line.split(' ')
|
||||
operands = operands.split(',')
|
||||
except:
|
||||
hex, insn = line.split(' ')
|
||||
operands = []
|
||||
|
||||
if insn[0] == '-':
|
||||
continue
|
||||
|
||||
ops = tuple(int(hex[i:i+2], 16) for i in xrange(0, len(hex), 2))
|
||||
if len(ops) == 1:
|
||||
ops, = ops
|
||||
|
||||
opcodes[ops] = insn, operands
|
||||
|
||||
__all__ = ('opcodes', )
|
||||
256
Core/Generators/opcodes.txt
Normal file
256
Core/Generators/opcodes.txt
Normal file
|
|
@ -0,0 +1,256 @@
|
|||
00 ADD Eb,Gb
|
||||
01 ADD Ev,Gv
|
||||
02 ADD Gb,Eb
|
||||
03 ADD Gv,Ev
|
||||
04 ADD AL,Ib
|
||||
05 ADD rAX,Iz
|
||||
06 PUSH ES
|
||||
07 POP ES
|
||||
10 ADC Eb,Gb
|
||||
11 ADC Ev,Gv
|
||||
12 ADC Gb,Eb
|
||||
13 ADC Gv,Ev
|
||||
14 ADC AL,Ib
|
||||
15 ADC rAX,Iz
|
||||
16 PUSH SS
|
||||
17 POP SS
|
||||
20 AND Eb,Gb
|
||||
21 AND Ev,Gv
|
||||
22 AND Gb,Eb
|
||||
23 AND Gv,Ev
|
||||
24 AND AL,Ib
|
||||
25 AND rAx,Iz
|
||||
26 -
|
||||
27 DAA
|
||||
30 XOR Eb,Gb
|
||||
31 XOR Ev,Gv
|
||||
32 XOR Gb,Eb
|
||||
33 XOR Gv,Ev
|
||||
34 XOR AL,Ib
|
||||
35 XOR rAX,Iz
|
||||
36 -
|
||||
37 AAA
|
||||
40 INC eAX
|
||||
41 INC eCX
|
||||
42 INC eDX
|
||||
43 INC eBX
|
||||
44 INC eSP
|
||||
45 INC eBP
|
||||
46 INC eSI
|
||||
47 INC eDI
|
||||
50 PUSH rAX
|
||||
51 PUSH rCX
|
||||
52 PUSH rDX
|
||||
53 PUSH rBX
|
||||
54 PUSH rSP
|
||||
55 PUSH rBP
|
||||
56 PUSH rSI
|
||||
57 PUSH rDI
|
||||
60 PUSHA
|
||||
61 POPA
|
||||
62 BOUND Gv,Ma
|
||||
63 ARPL Ew,Gw
|
||||
64 -
|
||||
65 -
|
||||
66 -
|
||||
67 -
|
||||
70 JO Jb
|
||||
71 JNO Jb
|
||||
72 JB Jb
|
||||
73 JNB Jb
|
||||
74 JZ Jb
|
||||
75 JNZ Jb
|
||||
76 JBE Jb
|
||||
77 JNBE Jb
|
||||
80 -group
|
||||
81 -group
|
||||
82 -group
|
||||
83 -group
|
||||
84 TEST Eb,Gb
|
||||
85 TEST Ev,Gv
|
||||
86 XCHG Eb,Gb
|
||||
87 XCHG Ev,Gv
|
||||
90 NOP
|
||||
91 XCHG rCX,rAX
|
||||
92 XCHG rDX,rAX
|
||||
93 XCHG rBX,rAX
|
||||
94 XCHG rSP,rAX
|
||||
95 XCHG rBP,rAX
|
||||
96 XCHG rSI,rAX
|
||||
97 XCHG rDI,rAX
|
||||
A0 MOV AL,Ov
|
||||
A1 MOV rAX,Ov
|
||||
A2 MOV Ov,AL
|
||||
A3 MOV Ov,rAX
|
||||
A4 MOVS Yb,Xb
|
||||
A5 MOVS Yv,Xv
|
||||
A6 CMPS Yb,Xb
|
||||
A7 CMPS Yv,Xv
|
||||
B0 MOV AL,Ib
|
||||
B1 MOV CL,Ib
|
||||
B2 MOV DL,Ib
|
||||
B3 MOV BL,Ib
|
||||
B4 MOV AH,Ib
|
||||
B5 MOV CH,Ib
|
||||
B6 MOV DH,Ib
|
||||
B7 MOV BH,Ib
|
||||
C0 -group
|
||||
C1 -group
|
||||
C2 RETnear_off Iw
|
||||
C3 RETnear
|
||||
C4 LES Gv,Mp
|
||||
C5 LDS Gv,Mp
|
||||
C6 -group
|
||||
C7 -group
|
||||
d0 -group
|
||||
d1 -group
|
||||
d2 -group
|
||||
d3 -group
|
||||
d4 AAM Ib
|
||||
d5 AAD Ib
|
||||
d6 SALC
|
||||
d7 XLAT
|
||||
e0 LOOPNZ Jb
|
||||
e1 LOOPZ Jb
|
||||
e2 LOOP Jb
|
||||
e3 JCXZ Jb
|
||||
e4 IN AL,Ib
|
||||
e5 IN eAX,Ib
|
||||
e6 OUT Ib,AL
|
||||
e7 OUT Ib,eAX
|
||||
f0 -
|
||||
f1 INT1
|
||||
f2 -
|
||||
f3 -
|
||||
f4 HLT
|
||||
f5 CMC
|
||||
f6 -group
|
||||
f7 -group
|
||||
08 OR Eb,Gb
|
||||
09 OR Ev,Gv
|
||||
0A OR Gb,Eb
|
||||
0B OR Gv,Ev
|
||||
0C OR AL,Ib
|
||||
0D OR rAX,Iz
|
||||
0E PUSH CS
|
||||
0F -group
|
||||
18 SBB Eb,Gb
|
||||
19 SBB Ev,Gv
|
||||
1A SBB Gb,Eb
|
||||
1B SBB Gv,Ev
|
||||
1C SBB AL,Ib
|
||||
1D SBB rAX,Iz
|
||||
1E PUSH DS
|
||||
1F POP DS
|
||||
28 SUB Eb,Gb
|
||||
29 SUB Ev,Gv
|
||||
2A SUB Gb,Eb
|
||||
2B SUB Gv,Ev
|
||||
2C SUB AL,Ib
|
||||
2D SUB rAX,Iz
|
||||
2E -
|
||||
2F DAS
|
||||
38 CMP Eb,Gb
|
||||
39 CMP Ev,Gv
|
||||
3A CMP Gb,Eb
|
||||
3B CMP Gv,Ev
|
||||
3C CMP AL,Ib
|
||||
3D CMP rAX,Iz
|
||||
3E -
|
||||
3F AAS
|
||||
48 DEC eAX
|
||||
49 DEC eCX
|
||||
4A DEC eDX
|
||||
4B DEC eBX
|
||||
4C DEC eSP
|
||||
4D DEC eBP
|
||||
4E DEC eSI
|
||||
4F DEC eDI
|
||||
58 POP rAX
|
||||
59 POP rCX
|
||||
5A POP rDX
|
||||
5B POP rBX
|
||||
5C POP rSP
|
||||
5D POP rBP
|
||||
5E POP rSI
|
||||
5F POP rDI
|
||||
68 PUSH Iz
|
||||
69 IMUL Gv,Ev,Iz
|
||||
6A PUSH Ib
|
||||
6B IMUL Gv,Ev,Ib
|
||||
6C INS Yb,DX
|
||||
6D INS Yz,DX
|
||||
6E OUTS DX,Xb
|
||||
6F OUTS DX,Xz
|
||||
78 JS Jb
|
||||
79 JNS Jb
|
||||
7A JP Jb
|
||||
7B JNP Jb
|
||||
7C JL Jb
|
||||
7D JNL Jb
|
||||
7E JLE Jb
|
||||
7F JNLE Jb
|
||||
88 MOV Eb,Gb
|
||||
89 MOV Ev,Gv
|
||||
8A MOV Gb,Eb
|
||||
8B MOV Gv,Ev
|
||||
8C --unknown
|
||||
8D LEA Gv,Ma
|
||||
8E --unknown
|
||||
8F -group
|
||||
98 CWDE
|
||||
99 CDQ
|
||||
9A CALL Ap
|
||||
9B WAIT
|
||||
9C PUSHF
|
||||
9D POPF
|
||||
9E SAHF
|
||||
9F LAHF
|
||||
A8 TEST AL,Ib
|
||||
A9 TEST rAX,Iz
|
||||
AA STOS Yb,AL
|
||||
AB STOS Yv,rAX
|
||||
AC LODS AL,Xb
|
||||
AD LODS rAX,Xv
|
||||
AE SCAS Yb,AL
|
||||
AF SCAS Yv,rAX
|
||||
B8 MOV rAX,Iv
|
||||
B9 MOV rCX,Iv
|
||||
BA MOV rDX,Iv
|
||||
BB MOV rBX,Iv
|
||||
BC MOV rSP,Iv
|
||||
BD MOV rBP,Iv
|
||||
BE MOV rSI,Iv
|
||||
BF MOV rDI,Iv
|
||||
C8 ENTER Iw,Ib
|
||||
C9 LEAVE
|
||||
CA RETfar_off Iw
|
||||
CB RETfar
|
||||
CC INT3
|
||||
CD INT Ib
|
||||
CE INTO
|
||||
CF IRET
|
||||
D8 -group
|
||||
D9 -group
|
||||
DA -group
|
||||
DB -group
|
||||
DC -group
|
||||
DD -group
|
||||
DE -group
|
||||
DF -group
|
||||
E8 CALL Jz
|
||||
E9 JMP Jz
|
||||
EA JMP Ap
|
||||
EB JMP Jb
|
||||
EC IN AL,DX
|
||||
ED IN eAX,DX
|
||||
EE OUT DX,AL
|
||||
EF OUT DX,eAX
|
||||
F8 CLC
|
||||
F9 STC
|
||||
FA CLI
|
||||
FB STI
|
||||
FC CLD
|
||||
FD STD
|
||||
FE -group
|
||||
FF -group
|
||||
|
|
@ -1 +1,6 @@
|
|||
env = Environment()
|
||||
|
||||
cgen = env.Command('Core/CPU/Interpreter/Interpreter_inst.cgen', 'Core/Generators/InterpreterGen.py', 'python $SOURCE > /dev/null')
|
||||
Depends(cgen, 'Core/Generators/opcodes.txt')
|
||||
|
||||
Program('interpreter', Glob('Core/CPU/Interpreter/*.cpp'))
|
||||
|
|
|
|||
Loading…
Reference in a new issue