mirror of
https://github.com/kinnay/Wii-U-Firmware-Emulator.git
synced 2024-05-31 18:47:27 -04:00
660 lines
17 KiB
C++
660 lines
17 KiB
C++
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#include "hardware/gpu.h"
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#include "physicalmemory.h"
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#include "common/exceptions.h"
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#include "common/endian.h"
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#include <cstring>
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void DCController::reset() {
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crtc_interrupt_control = 0;
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grph_enable = 0;
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grph_control = 0;
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grph_primary_surface_addr = 0;
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grph_secondary_surface_addr = 0;
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grph_dfq_status = 0;
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ovl_enable = 0;
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ovl_control1 = 0;
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ovl_surface_addr = 0;
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lut_autofill = 0;
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}
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uint32_t DCController::read(uint32_t addr) {
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switch (addr) {
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case D1CRTC_FORCE_COUNT_NOW_CNTL: return 0x10000;
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case D1CRTC_STATUS: return 1; //D1CRTC_V_BLANK
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case D1CRTC_INTERRUPT_CONTROL: return crtc_interrupt_control;
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case D1GRPH_ENABLE: return grph_enable;
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case D1GRPH_CONTROL: return grph_control;
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case D1GRPH_PRIMARY_SURFACE_ADDRESS: return grph_primary_surface_addr;
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case D1GRPH_SECONDARY_SURFACE_ADDRESS: return grph_secondary_surface_addr;
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case D1GRPH_DFQ_STATUS: return grph_dfq_status;
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case D1OVL_ENABLE: return ovl_enable;
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case D1OVL_CONTROL1: return ovl_control1;
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case D1OVL_SURFACE_ADDRESS: return ovl_surface_addr;
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case DC_LUT_AUTOFILL: return lut_autofill;
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}
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Logger::warning("Unknown dc read: 0x%X", addr);
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return 0;
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}
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void DCController::write(uint32_t addr, uint32_t value) {
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if (addr == D1CRTC_INTERRUPT_CONTROL) crtc_interrupt_control = value;
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else if (addr == D1GRPH_ENABLE) grph_enable = value;
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else if (addr == D1GRPH_CONTROL) grph_control = value;
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else if (addr == D1GRPH_PRIMARY_SURFACE_ADDRESS) grph_primary_surface_addr = value;
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else if (addr == D1GRPH_SECONDARY_SURFACE_ADDRESS) grph_secondary_surface_addr = value;
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else if (addr == D1GRPH_DFQ_CONTROL) {
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if (value & 1) {
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grph_dfq_status |= 0x100;
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}
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}
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else if (addr == D1GRPH_DFQ_STATUS) {
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if (value & 0x200) {
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grph_dfq_status &= ~0x100;
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}
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}
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else if (addr == D1OVL_ENABLE) ovl_enable = value;
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else if (addr == D1OVL_CONTROL1) ovl_control1 = value;
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else if (addr == D1OVL_SURFACE_ADDRESS) ovl_surface_addr = value;
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else if (addr == DC_LUT_PWL_DATA) {}
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else if (addr == DC_LUT_AUTOFILL) {
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if (value & 1) {
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lut_autofill = 2;
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}
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}
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else {
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Logger::warning("Unknown dc write: 0x%X (0x%08X)", addr, value);
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}
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}
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PM4Processor::PM4Processor(PhysicalMemory *physmem) {
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this->physmem = physmem;
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reset();
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}
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void PM4Processor::reset() {
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state = STATE_NEXT;
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args.clear();
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retired = false;
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}
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bool PM4Processor::check_interrupts() {
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bool ret = retired;
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retired = false;
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return ret;
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}
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void PM4Processor::process(uint32_t value) {
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if (state == STATE_NEXT) {
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int type = value >> 30;
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if (type == 0 || type == 3) {
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state = STATE_ARGUMENTS;
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argnum = ((value >> 16) & 0x3FFF) + 2;
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args.push_back(value);
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}
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else if (type == 2) {}
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else {
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Logger::warning("Unknown pm4 packet type: %i", type);
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}
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}
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else if (state == STATE_ARGUMENTS) {
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args.push_back(value);
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if (args.size() == argnum) {
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execute();
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args.clear();
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state = STATE_NEXT;
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}
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}
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}
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void PM4Processor::execute() {
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int type = args[0] >> 30;
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if (type == 0) {
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uint32_t addr = 0xC200000 | ((args[0] & 0xFFFF) << 2);
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for (int i = 1; i < args.size(); i++) {
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physmem->write<uint32_t>(addr, args[i]);
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addr += 4;
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}
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}
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else if (type == 3) {
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int opcode = (args[0] >> 8) & 0xFF;
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if (opcode == PM4_CONTEXT_CONTROL) {}
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else if (opcode == PM4_INDIRECT_BUFFER) {
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uint32_t addr = args.at(1) & ~3;
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uint32_t size = args.at(3);
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PM4Processor processor(physmem);
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for (uint32_t i = 0 ; i < size; i++) {
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uint32_t value = physmem->read<uint32_t>(addr + i * 4);
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processor.process(value);
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}
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}
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else if (opcode == PM4_MEM_WRITE) {
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uint32_t addr = args.at(1);
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uint32_t flags = args.at(2);
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uint32_t datalo = args.at(3);
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uint32_t datahi = args.at(4);
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if (flags & (1 << 18)) { // DATA32
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physmem->write<uint32_t>(addr & ~3, datalo);
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}
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else {
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physmem->write<uint64_t>(addr & ~7, datalo | ((uint64_t)datahi << 32));
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}
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}
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else if (opcode == PM4_ME_INITIALIZE) {} // Micro-engine initialization
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else if (opcode == PM4_EVENT_WRITE_EOP) {
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uint32_t addr = args.at(2);
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int datasel = args.at(3) >> 29;
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int intsel = (args.at(3) >> 24) & 3;
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uint32_t datalo = args.at(4);
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uint32_t datahi = args.at(5);
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if (intsel != 1) {
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if (datasel == 1) {
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physmem->write<uint32_t>(addr & ~3, datalo);
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}
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else if (datasel == 2) {
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addr &= ~7;
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physmem->write<uint32_t>(addr, datalo);
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physmem->write<uint32_t>(addr+4, datahi);
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}
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}
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if (intsel == 1 || intsel == 2) {
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retired = true;
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}
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}
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else if (opcode == PM4_SET_CONFIG_REG) {
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uint32_t addr = 0xC208000 + args.at(1) * 4;
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for (size_t i = 2; i < args.size(); i++) {
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physmem->write<uint32_t>(addr, args[i]);
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addr += 4;
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}
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}
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else if (opcode == PM4_SET_CONTEXT_REG) {
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uint32_t addr = 0xC228000 + args.at(1) * 4;
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for (size_t i = 2; i < args.size(); i++) {
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physmem->write<uint32_t>(addr, args[i]);
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addr += 4;
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}
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}
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else {
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Logger::warning("Unknown pm4 opcode: 0x%02X (%i dwords)", opcode, args.size());
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}
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}
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else {
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Logger::warning("Unknown pm4 packet type: %i", type);
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}
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}
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CPController::CPController(PhysicalMemory *physmem) :
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pm4(physmem)
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{
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this->physmem = physmem;
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}
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bool CPController::check_interrupts() {
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return pm4.check_interrupts();
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}
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void CPController::reset() {
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pm4.reset();
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memset(pfp_ucode_data, 0, sizeof(pfp_ucode_data));
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memset(me_ram_data, 0, sizeof(me_ram_data));
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pfp_ucode_addr = 0;
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me_ram_addr = 0;
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rb_base = 0;
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rb_cntl = 0;
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rb_rptr_addr = 0;
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rb_rptr = 0;
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rb_wptr = 0;
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rb_wptr_delay = 0;
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rb_rptr_wr = 0;
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}
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void CPController::process() {
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uint32_t bufsize = 2 << (rb_cntl & 0x3F);
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while (rb_rptr != rb_wptr) {
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uint32_t value = physmem->read<uint32_t>(rb_base + rb_rptr * 4);
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pm4.process(value);
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rb_rptr = (rb_rptr + 1) % bufsize;
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}
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if (!(rb_cntl & 0x10)) {
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physmem->write<uint32_t>(rb_rptr_addr & ~3, rb_rptr);
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}
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}
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uint32_t CPController::read(uint32_t addr) {
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switch (addr) {
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case CP_RB_BASE: return rb_base >> 8;
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case CP_RB_CNTL: return rb_cntl;
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case CP_RB_RPTR_ADDR: return rb_rptr_addr;
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case CP_RB_RPTR: return rb_rptr;
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case CP_RB_WPTR: return rb_wptr;
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case CP_RB_WPTR_DELAY: return rb_wptr_delay;
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case CP_PFP_UCODE_DATA: {
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uint32_t result = pfp_ucode_data[pfp_ucode_addr++];
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pfp_ucode_addr %= 0x350;
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return result;
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}
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case CP_ME_RAM_DATA: {
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uint32_t result = me_ram_data[me_ram_addr++];
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me_ram_addr %= 0x550;
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return result;
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}
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}
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Logger::warning("Unknown cp read: 0x%X", addr);
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return 0;
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}
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void CPController::write(uint32_t addr, uint32_t value) {
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if (addr == CP_RB_BASE) rb_base = value << 8;
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else if (addr == CP_RB_CNTL) rb_cntl = value;
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else if (addr == CP_RB_RPTR_ADDR) rb_rptr_addr = value;
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else if (addr == CP_RB_WPTR) {
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rb_wptr = value;
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if (rb_cntl & 1) {
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rb_rptr = rb_rptr_wr;
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}
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process();
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}
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else if (addr == CP_RB_WPTR_DELAY) rb_wptr_delay = value;
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else if (addr == CP_RB_RPTR_WR) rb_rptr_wr = value;
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else if (addr == CP_PFP_UCODE_ADDR) pfp_ucode_addr = value % 0x350;
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else if (addr == CP_PFP_UCODE_DATA) {
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pfp_ucode_data[pfp_ucode_addr++] = value;
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pfp_ucode_addr %= 0x350;
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}
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else if (addr == CP_ME_RAM_WADDR) me_ram_addr = value % 0x550;
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else if (addr == CP_ME_RAM_DATA) {
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me_ram_data[me_ram_addr++] = value;
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me_ram_addr %= 0x550;
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}
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else {
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Logger::warning("Unknown cp write: 0x%X (0x%08X)", addr, value);
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}
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}
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DMAProcessor::DMAProcessor(PhysicalMemory *physmem) {
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this->physmem = physmem;
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}
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void DMAProcessor::reset() {
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state = STATE_NEXT;
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trap = false;
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}
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bool DMAProcessor::check_interrupts() {
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bool ints = trap;
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trap = false;
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return ints;
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}
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int DMAProcessor::get_arg_num(Opcode opcode) {
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switch (opcode) {
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case DMA_PACKET_COPY: return 5;
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case DMA_PACKET_FENCE: return 4;
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case DMA_PACKET_TRAP: return 1;
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case DMA_PACKET_CONSTANT_FILL: return 4;
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case DMA_PACKET_NOP: return 1;
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}
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runtime_error("Unknown dma opcode: %i", opcode);
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return 0;
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}
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void DMAProcessor::process(uint32_t value) {
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if (state == STATE_NEXT) {
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args[0] = value;
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argidx = 1;
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Opcode opcode = (Opcode)(value >> 28);
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argnum = get_arg_num(opcode);
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if (argnum > 1) {
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state = STATE_ARGUMENTS;
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}
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else {
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execute();
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}
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}
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else if (state == STATE_ARGUMENTS) {
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args[argidx++] = value;
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if (argidx == argnum) {
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execute();
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}
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}
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}
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void DMAProcessor::execute() {
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Opcode opcode = (Opcode)(args[0] >> 28);
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if (opcode == DMA_PACKET_COPY) {
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int dwords = args[0] & 0xFFFF;
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uint32_t dst = args[1];
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uint32_t src = args[2];
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for (int i = 0; i < dwords; i++) {
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uint32_t value = physmem->read<uint32_t>(src + i * 4);
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physmem->write<uint32_t>(dst + i * 4, value);
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}
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}
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else if (opcode == DMA_PACKET_FENCE) {
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uint32_t addr = args[1];
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uint32_t value = args[3];
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physmem->write<uint32_t>(addr, value);
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}
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else if (opcode == DMA_PACKET_TRAP) trap = true;
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else if (opcode == DMA_PACKET_CONSTANT_FILL) {
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int dwords = args[0] & 0xFFFF;
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uint32_t addr = args[1];
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uint32_t value = Endian::swap32(args[2]);
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for (int i = 0; i < dwords; i++) {
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physmem->write(addr + i * 4, value);
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}
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}
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else if (opcode == DMA_PACKET_NOP) {}
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else {
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runtime_error("Unknown dma opcode: %i", opcode);
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}
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state = STATE_NEXT;
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}
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DMAController::DMAController(PhysicalMemory *physmem) :
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processor(physmem)
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{
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this->physmem = physmem;
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}
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void DMAController::reset() {
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processor.reset();
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rb_cntl = 0;
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rb_base = 0;
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rb_rptr = 0;
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rb_wptr = 0;
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rb_rptr_addr = 0;
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}
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bool DMAController::check_interrupts() {
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return processor.check_interrupts() && (rb_cntl & 1);
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}
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void DMAController::process() {
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if (rb_cntl & 1) {
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uint32_t size = 4 << ((rb_cntl >> 1) & 0x1F);
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while (rb_rptr != rb_wptr) {
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uint32_t value = physmem->read<uint32_t>(rb_base + rb_rptr);
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processor.process(value);
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rb_rptr = (rb_rptr + 4) % size;
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}
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if (rb_cntl & 0x1000) {
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physmem->write<uint32_t>(rb_rptr_addr, rb_rptr);
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}
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}
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}
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uint32_t DMAController::read(uint32_t addr) {
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switch (addr) {
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case DMA_RB_CNTL: return rb_cntl;
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case DMA_RB_BASE: return rb_base >> 8;
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case DMA_RB_RPTR: return rb_rptr;
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case DMA_RB_WPTR: return rb_wptr;
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case DMA_STATUS_REG: return 1; //idle
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}
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Logger::warning("Unknown dma read: 0x%X", addr);
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return 0;
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}
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void DMAController::write(uint32_t addr, uint32_t value) {
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if (addr == DMA_RB_CNTL) {
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rb_cntl = value;
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process();
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}
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else if (addr == DMA_RB_BASE) rb_base = value << 8;
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else if (addr == DMA_RB_RPTR) rb_rptr = value;
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else if (addr == DMA_RB_WPTR) {
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rb_wptr = value;
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process();
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}
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else if (addr == DMA_RB_RPTR_ADDR_HI) {}
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else if (addr == DMA_RB_RPTR_ADDR_LO) rb_rptr_addr = value;
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else {
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Logger::warning("Unknown dma write: 0x%X (0x%08X)", addr, value);
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}
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}
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void HDPHandle::reset() {}
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uint32_t HDPHandle::read(uint32_t addr) {
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Logger::warning("Unknown hdp handle read: 0x%X", addr);
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return 0;
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}
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void HDPHandle::write(uint32_t addr, uint32_t value) {
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if (addr == HDP_MAP_BASE) map_base = value;
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else if (addr == HDP_MAP_END) map_end = value;
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else if (addr == HDP_INPUT_ADDR) input_addr = value;
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else if (addr == HDP_CONFIG) config = value;
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else if (addr == HDP_DIMENSIONS) dimensions = value;
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else {
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Logger::warning("Unknown hdp handle write: 0x%X (0x%08X)", addr, value);
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}
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}
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bool HDPHandle::check(uint32_t addr) {
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return map_base != map_end && addr >= map_base && addr <= map_end;
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}
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void HDPController::reset() {
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for (int i = 0; i < 32; i++) {
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handles[i].reset();
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}
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}
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uint32_t HDPController::read(uint32_t addr) {
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if (HDP_HANDLE_START <= addr && addr < HDP_HANDLE_END) {
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addr -= HDP_HANDLE_START;
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return handles[addr / 0x18].read(addr % 0x18);
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}
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else if (HDP_TILING_START <= addr && addr < HDP_TILING_END) {
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HDPHandle *handle = find_handle(addr - HDP_TILING_START);
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if (!handle) {
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return 0;
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}
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Logger::warning("Tiling aperture not implemented");
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return 0;
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}
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Logger::warning("Unknown hdp read: 0x%X", addr);
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return 0;
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}
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void HDPController::write(uint32_t addr, uint32_t value) {
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if (HDP_HANDLE_START <= addr && addr < HDP_HANDLE_END) {
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addr -= HDP_HANDLE_START;
|
|
handles[addr / 0x18].write(addr % 0x18, value);
|
|
}
|
|
else {
|
|
Logger::warning("Unknown hdp write: 0x%X (0x%08X)", addr, value);
|
|
}
|
|
}
|
|
|
|
HDPHandle *HDPController::find_handle(uint32_t addr) {
|
|
for (int i = 0; i < 32; i++) {
|
|
if (handles[i].check(addr)) {
|
|
return &handles[i];
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
|
|
GPUController::GPUController(PhysicalMemory *physmem) :
|
|
cp(physmem),
|
|
dma(physmem)
|
|
{
|
|
this->physmem = physmem;
|
|
}
|
|
|
|
void GPUController::reset() {
|
|
memset(rlc_ucode_data, 0, sizeof(rlc_ucode_data));
|
|
memset(scratch, 0, sizeof(scratch));
|
|
|
|
scratch_umsk = 0;
|
|
scratch_addr = 0;
|
|
|
|
ih_rb_base = 0;
|
|
ih_rb_rptr = 0;
|
|
ih_rb_wptr_addr = 0;
|
|
|
|
rlc_ucode_addr = 0;
|
|
|
|
gb_tiling_config = 0;
|
|
cc_rb_backend_disable = 0;
|
|
|
|
dc0.reset();
|
|
dc1.reset();
|
|
cp.reset();
|
|
dma.reset();
|
|
hdp.reset();
|
|
}
|
|
|
|
void GPUController::trigger_irq(uint32_t type, uint32_t data1, uint32_t data2, uint32_t data3) {
|
|
uint32_t pos = physmem->read<uint32_t>(ih_rb_wptr_addr);
|
|
physmem->write<uint32_t>(ih_rb_base + pos, type);
|
|
physmem->write<uint32_t>(ih_rb_base + pos + 4, data1);
|
|
physmem->write<uint32_t>(ih_rb_base + pos + 8, data2);
|
|
physmem->write<uint32_t>(ih_rb_base + pos + 12, data3);
|
|
physmem->write<uint32_t>(ih_rb_wptr_addr, pos + 16);
|
|
}
|
|
|
|
void GPUController::update() {
|
|
timer++;
|
|
if (timer == 35000) { // Trigger vsync
|
|
if (dc0.crtc_interrupt_control & 0x01000000) trigger_irq(2, 3, 0, 0);
|
|
if (dc1.crtc_interrupt_control & 0x01000000) trigger_irq(6, 3, 0, 0);
|
|
timer = 0;
|
|
}
|
|
|
|
if (dma.check_interrupts()) {
|
|
trigger_irq(0xE0, 0, 0, 0);
|
|
}
|
|
if (cp.check_interrupts()) {
|
|
trigger_irq(0xB5, 0, 0, 0);
|
|
}
|
|
}
|
|
|
|
bool GPUController::check_interrupts() {
|
|
return ih_rb_wptr_addr && physmem->read<uint32_t>(ih_rb_wptr_addr) != ih_rb_rptr;
|
|
}
|
|
|
|
uint32_t GPUController::read(uint32_t addr) {
|
|
switch (addr) {
|
|
case GPU_IH_RB_BASE: return ih_rb_base >> 8;
|
|
case GPU_IH_RB_RPTR: return ih_rb_rptr;
|
|
case GPU_IH_RB_WPTR_ADDR_LO: return ih_rb_wptr_addr;
|
|
case GPU_IH_STATUS: return 5;
|
|
|
|
case GPU_RLC_UCODE_DATA: {
|
|
uint32_t result = rlc_ucode_data[rlc_ucode_addr++];
|
|
rlc_ucode_addr %= 0x400;
|
|
return result;
|
|
}
|
|
|
|
case GPU_SCRATCH_UMSK: return scratch_umsk;
|
|
case GPU_SCRATCH_ADDR: return scratch_addr >> 8;
|
|
|
|
case GPU_GB_TILING_CONFIG: return gb_tiling_config;
|
|
case GPU_CC_RB_BACKEND_DISABLE: return cc_rb_backend_disable;
|
|
}
|
|
|
|
if (GPU_SCRATCH_START <= addr && addr < GPU_SCRATCH_END) {
|
|
uint32_t index = (addr - GPU_SCRATCH_START) / 4;
|
|
return scratch[index];
|
|
}
|
|
|
|
if (GPU_DC0_START <= addr && addr < GPU_DC0_END) return dc0.read(addr - GPU_DC0_START);
|
|
if (GPU_DC1_START <= addr && addr < GPU_DC1_END) return dc1.read(addr - GPU_DC1_START);
|
|
if (GPU_CP_START <= addr && addr < GPU_CP_END) return cp.read(addr);
|
|
if (GPU_DMA_START <= addr && addr < GPU_DMA_END) return dma.read(addr);
|
|
if (GPU_HDP_START <= addr && addr < GPU_HDP_END) return hdp.read(addr);
|
|
if (GPU_TILING_START <= addr && addr < GPU_TILING_END) return hdp.read(addr);
|
|
|
|
Logger::warning("Unknown gpu read: 0x%X", addr);
|
|
return 0;
|
|
}
|
|
|
|
void GPUController::write(uint32_t addr, uint32_t value) {
|
|
if (addr == GPU_IH_RB_BASE) ih_rb_base = value << 8;
|
|
else if (addr == GPU_IH_RB_RPTR) ih_rb_rptr = value;
|
|
else if (addr == GPU_IH_RB_WPTR_ADDR_LO) ih_rb_wptr_addr = value;
|
|
|
|
else if (addr == GPU_RLC_UCODE_ADDR) rlc_ucode_addr = value % 0x400;
|
|
else if (addr == GPU_RLC_UCODE_DATA) {
|
|
rlc_ucode_data[rlc_ucode_addr++] = value;
|
|
rlc_ucode_addr %= 0x400;
|
|
}
|
|
|
|
else if (addr == GPU_GRBM_SOFT_RESET) {
|
|
if (value & 1) {
|
|
cp.reset();
|
|
}
|
|
}
|
|
|
|
else if (addr == GPU_WAIT_UNTIL) {}
|
|
|
|
else if (addr == GPU_SCRATCH_UMSK) scratch_umsk = value;
|
|
else if (addr == GPU_SCRATCH_ADDR) scratch_addr = value << 8;
|
|
|
|
else if (addr == GPU_GB_TILING_CONFIG) gb_tiling_config = value;
|
|
else if (addr == GPU_CC_RB_BACKEND_DISABLE) cc_rb_backend_disable = value;
|
|
|
|
else if (GPU_SCRATCH_START <= addr && addr < GPU_SCRATCH_END) {
|
|
uint32_t index = (addr - GPU_SCRATCH_START) / 4;
|
|
scratch[index] = value;
|
|
if (scratch_umsk & (1 << index)) {
|
|
physmem->write<uint32_t>(scratch_addr + index * 4, value);
|
|
}
|
|
}
|
|
|
|
else if (GPU_DC0_START <= addr && addr < GPU_DC0_END) dc0.write(addr - GPU_DC0_START, value);
|
|
else if (GPU_DC1_START <= addr && addr < GPU_DC1_END) dc1.write(addr - GPU_DC1_START, value);
|
|
else if (GPU_CP_START <= addr && addr < GPU_CP_END) cp.write(addr, value);
|
|
else if (GPU_DMA_START <= addr && addr < GPU_DMA_END) dma.write(addr, value);
|
|
else if (GPU_HDP_START <= addr && addr < GPU_HDP_END) hdp.write(addr, value);
|
|
else if (GPU_TILING_START <= addr && addr < GPU_TILING_END) hdp.write(addr, value);
|
|
|
|
else {
|
|
Logger::warning("Unknown gpu write: 0x%X (0x%08X)", addr, value);
|
|
}
|
|
}
|