mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2024-06-11 17:07:16 -04:00
79770f6207
Manually cherry-picked ares commit 70f361094b.
Co-Authored-By: absindx <59403574+absindx@users.noreply.github.com>
140 lines
3.8 KiB
C++
140 lines
3.8 KiB
C++
auto SA1::idle() -> void {
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step();
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}
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//RTx, JMx, JSx
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auto SA1::idleJump() -> void {
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//ROM access penalty cycle: does not apply to BWRAM or IRAM
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if((r.pc.d & 0x408000) == 0x008000 //00-3f,80-bf:8000-ffff
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|| (r.pc.d & 0xc00000) == 0xc00000 //c0-ff:0000-ffff
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) {
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step();
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if(rom.conflict()) step();
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}
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}
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//Bxx
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auto SA1::idleBranch() -> void {
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if(r.pc.d & 1) idleJump();
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}
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auto SA1::read(uint address) -> uint8 {
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r.mar = address;
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uint8 data = r.mdr;
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if((address & 0x40fe00) == 0x002200 //00-3f,80-bf:2200-23ff
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) {
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step();
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return r.mdr = readIOSA1(address, data);
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}
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if((address & 0x408000) == 0x008000 //00-3f,80-bf:8000-ffff
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|| (address & 0xc00000) == 0xc00000 //c0-ff:0000-ffff
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) {
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step();
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if(rom.conflict()) step();
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return r.mdr = rom.readSA1(address, data);
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}
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if((address & 0x40e000) == 0x006000 //00-3f,80-bf:6000-7fff
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|| (address & 0xe00000) == 0x400000 //40-5f:0000-ffff
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|| (address & 0xf00000) == 0x600000 //60-6f:0000-ffff
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) {
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step();
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step();
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if(bwram.conflict()) step();
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if(bwram.conflict()) step();
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if((address & 1 << 22) && (address & 1 << 21)) return r.mdr = bwram.readBitmap(address, data);
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if((address & 1 << 22)) return r.mdr = bwram.readLinear(address, data);
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return r.mdr = bwram.readSA1(address, data);
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}
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if((address & 0x40f800) == 0x000000 //00-3f,80-bf:0000-07ff
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|| (address & 0x40f800) == 0x003000 //00-3f,80-bf:3000-37ff
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) {
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step();
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if(iram.conflict()) step();
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if(iram.conflict()) step();
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return r.mdr = iram.readSA1(address, data);
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}
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step();
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return data;
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}
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auto SA1::write(uint address, uint8 data) -> void {
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r.mar = address;
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r.mdr = data;
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if((address & 0x40fe00) == 0x002200 //00-3f,80-bf:2200-23ff
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) {
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step();
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return writeIOSA1(address, data);
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}
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if((address & 0x408000) == 0x008000 //00-3f,80-bf:8000-ffff
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|| (address & 0xc00000) == 0xc00000 //c0-ff:0000-ffff
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) {
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step();
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if(rom.conflict()) step();
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return rom.writeSA1(address, data);
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}
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if((address & 0x40e000) == 0x006000 //00-3f,80-bf:6000-7fff
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|| (address & 0xe00000) == 0x400000 //40-5f:0000-ffff
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|| (address & 0xf00000) == 0x600000 //60-6f:0000-ffff
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) {
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step();
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step();
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if(bwram.conflict()) step();
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if(bwram.conflict()) step();
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if((address & 1 << 22) && (address & 1 << 21)) return bwram.writeBitmap(address, data);
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if((address & 1 << 22)) return bwram.writeLinear(address, data);
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return bwram.writeSA1(address, data);
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}
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if((address & 0x40f800) == 0x000000 //00-3f,80-bf:0000-07ff
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|| (address & 0x40f800) == 0x003000 //00-3f,80-bf:3000-37ff
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) {
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step();
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if(iram.conflict()) step();
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if(iram.conflict()) step();
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return iram.writeSA1(address, data);
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}
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step();
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return;
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}
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//$230c (VDPL), $230d (VDPH) use this bus to read variable-length data.
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//this is used both to keep VBR-reads from accessing MMIO registers, and
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//to avoid syncing the S-CPU and SA-1*; as both chips are able to access
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//these ports.
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auto SA1::readVBR(uint address, uint8 data) -> uint8 {
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if((address & 0x408000) == 0x008000 //00-3f,80-bf:8000-ffff
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|| (address & 0xc00000) == 0xc00000 //c0-ff:0000-ffff
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) {
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return rom.readSA1(address, data);
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}
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if((address & 0x40e000) == 0x006000 //00-3f,80-bf:6000-7fff
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|| (address & 0xf00000) == 0x400000 //40-4f:0000-ffff
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) {
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return bwram.read(address, data);
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}
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if((address & 0x40f800) == 0x000000 //00-3f,80-bf:0000-07ff
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|| (address & 0x40f800) == 0x003000 //00-3f,80-bf:3000-37ff
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) {
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return iram.read(address, data);
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}
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return 0xff;
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}
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auto SA1::readDisassembler(uint address) -> uint8 {
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//TODO: this is a hack; SA1::read() advances the clock; whereas Bus::read() does not
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//the CPU and SA1 bus are identical for ROM, but have differences in BWRAM and IRAM
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return bus.read(address, r.mdr);
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}
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