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rsp: Implement CTC2.

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This commit is contained in:
Tyler Stachecki 2016-06-29 21:38:25 -04:00
parent 91926630e8
commit 91b18f2644
5 changed files with 51 additions and 1 deletions
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27
arch/x86_64/rsp/rsp.c
View file

@ -227,6 +227,33 @@ static inline __m128i sse2_pshufb(__m128i v, const uint16_t *keys) {
// Deallocates dynarec buffers for SSE2.
void arch_rsp_destroy(struct rsp *rsp) {}
// Uses a LUT to populate flag registers.
void rsp_set_flags(uint16_t *flags, uint16_t rt) {
unsigned i;
static const uint16_t array[16][4] = {
{0x0000, 0x0000, 0x0000, 0x0000},
{0xFFFF, 0x0000, 0x0000, 0x0000},
{0x0000, 0xFFFF, 0x0000, 0x0000},
{0xFFFF, 0xFFFF, 0x0000, 0x0000},
{0x0000, 0x0000, 0xFFFF, 0x0000},
{0xFFFF, 0x0000, 0xFFFF, 0x0000},
{0x0000, 0xFFFF, 0xFFFF, 0x0000},
{0xFFFF, 0xFFFF, 0xFFFF, 0x0000},
{0x0000, 0x0000, 0x0000, 0xFFFF},
{0xFFFF, 0x0000, 0x0000, 0xFFFF},
{0x0000, 0xFFFF, 0x0000, 0xFFFF},
{0xFFFF, 0xFFFF, 0x0000, 0xFFFF},
{0x0000, 0x0000, 0xFFFF, 0xFFFF},
{0xFFFF, 0x0000, 0xFFFF, 0xFFFF},
{0x0000, 0xFFFF, 0xFFFF, 0xFFFF},
{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF},
};
for (i = 0; i < 4; i++, rt >>= 4)
memcpy(flags + i * 4, array[rt & 0xF], sizeof(array[0]));
}
// Allocates dynarec buffers for SSE2.
int arch_rsp_init(struct rsp *rsp) { return 0; }

2
arch/x86_64/rsp/rsp.h
View file

@ -182,6 +182,8 @@ static inline int16_t rsp_get_flags(const uint16_t *flags) {
);
}
void rsp_set_flags(uint16_t *flags, uint16_t rt);
// Zeroes out a vector register.
static inline __m128i rsp_vzero(void) {
return _mm_setzero_si128();

20
rsp/cp2.c
View file

@ -24,6 +24,7 @@ void RSP_CFC2(struct rsp *rsp,
dest = GET_RT(iw);
rd = GET_RD(iw);
// TODO: verify on hardware
if ((src = rd & 0x3) == 0x3)
src = 2;
@ -31,6 +32,25 @@ void RSP_CFC2(struct rsp *rsp,
exdf_latch->result.dest = dest;
}
//
// CTC2
//
void RSP_CTC2(struct rsp *rsp,
uint32_t iw, uint32_t rs, uint32_t rt) {
struct rsp_cp2 *cp2 = &rsp->cp2;
unsigned rd, dest;
rd = GET_RD(iw);
// TODO: verify on hardware
if ((dest = rd & 0x3) >= 0x2) {
rt &= 0xFF;
dest = 2;
}
rsp_set_flags(cp2->flags[dest].e, rt);
}
//
// MFC2
//

1
rsp/cp2.h
View file

@ -51,6 +51,7 @@ struct rsp_cp2 {
};
void RSP_CFC2(struct rsp *rsp, uint32_t iw, uint32_t rs, uint32_t rt);
void RSP_CTC2(struct rsp *rsp, uint32_t iw, uint32_t rs, uint32_t rt);
void RSP_MFC2(struct rsp *rsp, uint32_t iw, uint32_t rs, uint32_t rt);
void RSP_MTC2(struct rsp *rsp, uint32_t iw, uint32_t rs, uint32_t rt);

2
rsp/opcodes_priv.h
View file

@ -69,7 +69,7 @@
#define MTC0 RSP_BUILD_OP(MTC0, MTC0, INFO1(NEEDRT))
#define CFC2 RSP_BUILD_OP(CFC2, CFC2, INFO1(NONE))
#define CTC2 RSP_BUILD_OP(CTC2, INVALID, INFO1(NONE))
#define CTC2 RSP_BUILD_OP(CTC2, CTC2, INFO1(NEEDRT))
#define MFC2 RSP_BUILD_OP(MFC2, MFC2, INFO1(NONE))
#define MTC2 RSP_BUILD_OP(MTC2, MTC2, INFO1(NEEDRT))