mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2024-06-02 19:47:32 -04:00
998 lines
31 KiB
C++
998 lines
31 KiB
C++
/*
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Copyright 2016-2022 melonDS team, RSDuck
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include "ARMJIT_Compiler.h"
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#include "../ARMJIT_Internal.h"
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#include "../ARMInterpreter.h"
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#include "../ARMJIT.h"
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#include "../NDS.h"
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#if defined(__SWITCH__)
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#include <switch.h>
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extern char __start__;
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#elif defined(_WIN32)
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#include <windows.h>
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#else
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#include <sys/mman.h>
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#include <unistd.h>
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#endif
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#include <stdlib.h>
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using namespace Arm64Gen;
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extern "C" void ARM_Ret();
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namespace melonDS
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{
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/*
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Recompiling classic ARM to ARMv8 code is at the same time
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easier and trickier than compiling to a less related architecture
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like x64. At one hand you can translate a lot of instructions directly.
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But at the same time, there are a ton of exceptions, like for
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example ADD and SUB can't have a RORed second operand on ARMv8.
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While writing a JIT when an instruction is recompiled into multiple ones
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not to write back until you've read all the other operands!
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*/
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template <>
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const ARM64Reg RegisterCache<Compiler, ARM64Reg>::NativeRegAllocOrder[] =
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{
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W19, W20, W21, W22, W23, W24, W25,
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W8, W9, W10, W11, W12, W13, W14, W15
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};
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template <>
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const int RegisterCache<Compiler, ARM64Reg>::NativeRegsAvailable = 15;
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const BitSet32 CallerSavedPushRegs({W8, W9, W10, W11, W12, W13, W14, W15});
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const int JitMemSize = 16 * 1024 * 1024;
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#ifndef __SWITCH__
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u8 JitMem[JitMemSize];
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#endif
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void Compiler::MovePC()
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{
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ADD(MapReg(15), MapReg(15), Thumb ? 2 : 4);
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}
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void Compiler::A_Comp_MRS()
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{
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Comp_AddCycles_C();
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ARM64Reg rd = MapReg(CurInstr.A_Reg(12));
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if (CurInstr.Instr & (1 << 22))
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{
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ANDI2R(W5, RCPSR, 0x1F);
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MOVI2R(W3, 0);
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MOVI2R(W1, 15 - 8);
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BL(ReadBanked);
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MOV(rd, W3);
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}
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else
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MOV(rd, RCPSR);
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}
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void UpdateModeTrampoline(ARM* arm, u32 oldmode, u32 newmode)
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{
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arm->UpdateMode(oldmode, newmode);
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}
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void Compiler::A_Comp_MSR()
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{
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Comp_AddCycles_C();
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ARM64Reg val;
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if (CurInstr.Instr & (1 << 25))
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{
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val = W0;
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MOVI2R(val, melonDS::ROR((CurInstr.Instr & 0xFF), ((CurInstr.Instr >> 7) & 0x1E)));
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}
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else
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{
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val = MapReg(CurInstr.A_Reg(0));
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}
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u32 mask = 0;
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if (CurInstr.Instr & (1<<16)) mask |= 0x000000FF;
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if (CurInstr.Instr & (1<<17)) mask |= 0x0000FF00;
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if (CurInstr.Instr & (1<<18)) mask |= 0x00FF0000;
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if (CurInstr.Instr & (1<<19)) mask |= 0xFF000000;
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if (CurInstr.Instr & (1 << 22))
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{
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ANDI2R(W5, RCPSR, 0x1F);
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MOVI2R(W3, 0);
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MOVI2R(W1, 15 - 8);
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BL(ReadBanked);
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MOVI2R(W1, mask);
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MOVI2R(W2, mask & 0xFFFFFF00);
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ANDI2R(W5, RCPSR, 0x1F);
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CMP(W5, 0x10);
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CSEL(W1, W2, W1, CC_EQ);
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BIC(W3, W3, W1);
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AND(W0, val, W1);
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ORR(W3, W3, W0);
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MOVI2R(W1, 15 - 8);
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BL(WriteBanked);
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}
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else
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{
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mask &= 0xFFFFFFDF;
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CPSRDirty = true;
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if ((mask & 0xFF) == 0)
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{
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ANDI2R(RCPSR, RCPSR, ~mask);
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ANDI2R(W0, val, mask);
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ORR(RCPSR, RCPSR, W0);
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}
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else
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{
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MOVI2R(W2, mask);
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MOVI2R(W3, mask & 0xFFFFFF00);
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ANDI2R(W1, RCPSR, 0x1F);
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// W1 = first argument
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CMP(W1, 0x10);
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CSEL(W2, W3, W2, CC_EQ);
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BIC(RCPSR, RCPSR, W2);
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AND(W0, val, W2);
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ORR(RCPSR, RCPSR, W0);
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MOV(W2, RCPSR);
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MOV(X0, RCPU);
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PushRegs(true, true);
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QuickCallFunction(X3, UpdateModeTrampoline);
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PopRegs(true, true);
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}
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}
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}
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void Compiler::PushRegs(bool saveHiRegs, bool saveRegsToBeChanged, bool allowUnload)
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{
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BitSet32 loadedRegs(RegCache.LoadedRegs);
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if (saveHiRegs)
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{
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BitSet32 hiRegsLoaded(RegCache.LoadedRegs & 0x7F00);
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for (int reg : hiRegsLoaded)
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{
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if (Thumb || CurInstr.Cond() == 0xE)
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RegCache.UnloadRegister(reg);
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else
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SaveReg(reg, RegCache.Mapping[reg]);
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// prevent saving the register twice
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loadedRegs[reg] = false;
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}
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}
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for (int reg : loadedRegs)
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{
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if (CallerSavedPushRegs[RegCache.Mapping[reg]]
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&& (saveRegsToBeChanged || !((1<<reg) & CurInstr.Info.DstRegs && !((1<<reg) & CurInstr.Info.SrcRegs))))
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{
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if ((Thumb || CurInstr.Cond() == 0xE) && !((1 << reg) & (CurInstr.Info.DstRegs|CurInstr.Info.SrcRegs)) && allowUnload)
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RegCache.UnloadRegister(reg);
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else
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SaveReg(reg, RegCache.Mapping[reg]);
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}
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}
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}
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void Compiler::PopRegs(bool saveHiRegs, bool saveRegsToBeChanged)
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{
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BitSet32 loadedRegs(RegCache.LoadedRegs);
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for (int reg : loadedRegs)
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{
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if ((saveHiRegs && reg >= 8 && reg < 15)
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|| (CallerSavedPushRegs[RegCache.Mapping[reg]]
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&& (saveRegsToBeChanged || !((1<<reg) & CurInstr.Info.DstRegs && !((1<<reg) & CurInstr.Info.SrcRegs)))))
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{
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LoadReg(reg, RegCache.Mapping[reg]);
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}
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}
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}
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Compiler::Compiler(melonDS::NDS& nds) : Arm64Gen::ARM64XEmitter(), NDS(nds)
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{
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#ifdef __SWITCH__
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JitRWBase = aligned_alloc(0x1000, JitMemSize);
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JitRXStart = (u8*)&__start__ - JitMemSize - 0x1000;
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virtmemLock();
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JitRWStart = virtmemFindAslr(JitMemSize, 0x1000);
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MemoryInfo info = {0};
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u32 pageInfo = {0};
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int i = 0;
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while (JitRXStart != NULL)
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{
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svcQueryMemory(&info, &pageInfo, (u64)JitRXStart);
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if (info.type != MemType_Unmapped)
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JitRXStart = (void*)((u8*)info.addr - JitMemSize - 0x1000);
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else
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break;
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if (i++ > 8)
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{
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Log(LogLevel::Error, "couldn't find unmapped place for jit memory\n");
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JitRXStart = NULL;
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}
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}
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assert(JitRXStart != NULL);
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bool succeded = R_SUCCEEDED(svcMapProcessCodeMemory(envGetOwnProcessHandle(), (u64)JitRXStart, (u64)JitRWBase, JitMemSize));
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assert(succeded);
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succeded = R_SUCCEEDED(svcSetProcessMemoryPermission(envGetOwnProcessHandle(), (u64)JitRXStart, JitMemSize, Perm_Rx));
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assert(succeded);
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succeded = R_SUCCEEDED(svcMapProcessMemory(JitRWStart, envGetOwnProcessHandle(), (u64)JitRXStart, JitMemSize));
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assert(succeded);
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virtmemUnlock();
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SetCodeBase((u8*)JitRWStart, (u8*)JitRXStart);
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JitMemMainSize = JitMemSize;
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#else
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#ifdef _WIN32
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SYSTEM_INFO sysInfo;
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GetSystemInfo(&sysInfo);
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u64 pageSize = (u64)sysInfo.dwPageSize;
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#else
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u64 pageSize = sysconf(_SC_PAGE_SIZE);
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#endif
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u8* pageAligned = (u8*)(((u64)JitMem & ~(pageSize - 1)) + pageSize);
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u64 alignedSize = (((u64)JitMem + sizeof(JitMem)) & ~(pageSize - 1)) - (u64)pageAligned;
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#if defined(_WIN32)
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DWORD dummy;
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VirtualProtect(pageAligned, alignedSize, PAGE_EXECUTE_READWRITE, &dummy);
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#elif defined(__APPLE__)
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pageAligned = (u8*)mmap(NULL, 1024*1024*16, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS | MAP_JIT,-1, 0);
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nds.JIT.JitEnableWrite();
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#else
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mprotect(pageAligned, alignedSize, PROT_EXEC | PROT_READ | PROT_WRITE);
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#endif
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SetCodeBase(pageAligned, pageAligned);
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JitMemMainSize = alignedSize;
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#endif
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SetCodePtr(0);
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for (int i = 0; i < 3; i++)
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{
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JumpToFuncs9[i] = Gen_JumpTo9(i);
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JumpToFuncs7[i] = Gen_JumpTo7(i);
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}
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/*
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W4 - whether the register was written to
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W5 - mode
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W1 - reg num
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W3 - in/out value of reg
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*/
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{
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ReadBanked = GetRXPtr();
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ADD(X2, RCPU, X1, ArithOption(X2, ST_LSL, 2));
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CMP(W5, 0x11);
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FixupBranch fiq = B(CC_EQ);
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SUBS(W1, W1, 13 - 8);
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ADD(X2, RCPU, X1, ArithOption(X2, ST_LSL, 2));
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FixupBranch notEverything = B(CC_LT);
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CMP(W5, 0x12);
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FixupBranch irq = B(CC_EQ);
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CMP(W5, 0x13);
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FixupBranch svc = B(CC_EQ);
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CMP(W5, 0x17);
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FixupBranch abt = B(CC_EQ);
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CMP(W5, 0x1B);
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FixupBranch und = B(CC_EQ);
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SetJumpTarget(notEverything);
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RET();
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SetJumpTarget(fiq);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_FIQ));
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RET();
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SetJumpTarget(irq);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_IRQ));
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RET();
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SetJumpTarget(svc);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_SVC));
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RET();
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SetJumpTarget(abt);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_ABT));
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RET();
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SetJumpTarget(und);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_UND));
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RET();
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}
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{
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WriteBanked = GetRXPtr();
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ADD(X2, RCPU, X1, ArithOption(X2, ST_LSL, 2));
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CMP(W5, 0x11);
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FixupBranch fiq = B(CC_EQ);
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SUBS(W1, W1, 13 - 8);
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ADD(X2, RCPU, X1, ArithOption(X2, ST_LSL, 2));
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FixupBranch notEverything = B(CC_LT);
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CMP(W5, 0x12);
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FixupBranch irq = B(CC_EQ);
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CMP(W5, 0x13);
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FixupBranch svc = B(CC_EQ);
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CMP(W5, 0x17);
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FixupBranch abt = B(CC_EQ);
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CMP(W5, 0x1B);
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FixupBranch und = B(CC_EQ);
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SetJumpTarget(notEverything);
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MOVI2R(W4, 0);
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RET();
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SetJumpTarget(fiq);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_FIQ));
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MOVI2R(W4, 1);
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RET();
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SetJumpTarget(irq);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_IRQ));
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MOVI2R(W4, 1);
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RET();
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SetJumpTarget(svc);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_SVC));
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MOVI2R(W4, 1);
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RET();
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SetJumpTarget(abt);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_ABT));
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MOVI2R(W4, 1);
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RET();
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SetJumpTarget(und);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_UND));
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MOVI2R(W4, 1);
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RET();
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}
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for (int consoleType = 0; consoleType < 2; consoleType++)
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{
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for (int num = 0; num < 2; num++)
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{
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for (int size = 0; size < 3; size++)
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{
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for (int reg = 0; reg < 32; reg++)
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{
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if (!(reg == W4 || (reg >= W8 && reg <= W15) || (reg >= W19 && reg <= W25)))
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continue;
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ARM64Reg rdMapped = (ARM64Reg)reg;
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PatchedStoreFuncs[consoleType][num][size][reg] = GetRXPtr();
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if (num == 0)
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{
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MOV(X1, RCPU);
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MOV(W2, rdMapped);
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}
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else
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{
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MOV(W1, rdMapped);
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}
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ABI_PushRegisters(BitSet32({30}) | CallerSavedPushRegs);
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if (consoleType == 0)
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{
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switch ((8 << size) | num)
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{
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case 32: QuickCallFunction(X3, SlowWrite9<u32, 0>); break;
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case 33: QuickCallFunction(X3, SlowWrite7<u32, 0>); break;
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case 16: QuickCallFunction(X3, SlowWrite9<u16, 0>); break;
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case 17: QuickCallFunction(X3, SlowWrite7<u16, 0>); break;
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case 8: QuickCallFunction(X3, SlowWrite9<u8, 0>); break;
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case 9: QuickCallFunction(X3, SlowWrite7<u8, 0>); break;
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}
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}
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else
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{
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switch ((8 << size) | num)
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{
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case 32: QuickCallFunction(X3, SlowWrite9<u32, 1>); break;
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case 33: QuickCallFunction(X3, SlowWrite7<u32, 1>); break;
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case 16: QuickCallFunction(X3, SlowWrite9<u16, 1>); break;
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case 17: QuickCallFunction(X3, SlowWrite7<u16, 1>); break;
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case 8: QuickCallFunction(X3, SlowWrite9<u8, 1>); break;
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case 9: QuickCallFunction(X3, SlowWrite7<u8, 1>); break;
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}
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}
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ABI_PopRegisters(BitSet32({30}) | CallerSavedPushRegs);
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RET();
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for (int signextend = 0; signextend < 2; signextend++)
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{
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PatchedLoadFuncs[consoleType][num][size][signextend][reg] = GetRXPtr();
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if (num == 0)
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MOV(X1, RCPU);
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ABI_PushRegisters(BitSet32({30}) | CallerSavedPushRegs);
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if (consoleType == 0)
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{
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switch ((8 << size) | num)
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{
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case 32: QuickCallFunction(X3, SlowRead9<u32, 0>); break;
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case 33: QuickCallFunction(X3, SlowRead7<u32, 0>); break;
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case 16: QuickCallFunction(X3, SlowRead9<u16, 0>); break;
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case 17: QuickCallFunction(X3, SlowRead7<u16, 0>); break;
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case 8: QuickCallFunction(X3, SlowRead9<u8, 0>); break;
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case 9: QuickCallFunction(X3, SlowRead7<u8, 0>); break;
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}
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}
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else
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{
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switch ((8 << size) | num)
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{
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case 32: QuickCallFunction(X3, SlowRead9<u32, 1>); break;
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case 33: QuickCallFunction(X3, SlowRead7<u32, 1>); break;
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case 16: QuickCallFunction(X3, SlowRead9<u16, 1>); break;
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case 17: QuickCallFunction(X3, SlowRead7<u16, 1>); break;
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case 8: QuickCallFunction(X3, SlowRead9<u8, 1>); break;
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case 9: QuickCallFunction(X3, SlowRead7<u8, 1>); break;
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}
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}
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ABI_PopRegisters(BitSet32({30}) | CallerSavedPushRegs);
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if (size == 32)
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MOV(rdMapped, W0);
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else if (signextend)
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SBFX(rdMapped, W0, 0, 8 << size);
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else
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UBFX(rdMapped, W0, 0, 8 << size);
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RET();
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}
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}
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}
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}
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}
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FlushIcache();
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JitMemSecondarySize = 1024*1024*4;
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JitMemMainSize -= GetCodeOffset();
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JitMemMainSize -= JitMemSecondarySize;
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SetCodeBase((u8*)GetRWPtr(), (u8*)GetRXPtr());
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}
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Compiler::~Compiler()
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|
{
|
|
#ifdef __SWITCH__
|
|
if (JitRWStart != NULL)
|
|
{
|
|
bool succeded = R_SUCCEEDED(svcUnmapProcessMemory(JitRWStart, envGetOwnProcessHandle(), (u64)JitRXStart, JitMemSize));
|
|
assert(succeded);
|
|
succeded = R_SUCCEEDED(svcUnmapProcessCodeMemory(envGetOwnProcessHandle(), (u64)JitRXStart, (u64)JitRWBase, JitMemSize));
|
|
assert(succeded);
|
|
free(JitRWBase);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void Compiler::LoadCycles()
|
|
{
|
|
LDR(INDEX_UNSIGNED, RCycles, RCPU, offsetof(ARM, Cycles));
|
|
}
|
|
|
|
void Compiler::SaveCycles()
|
|
{
|
|
STR(INDEX_UNSIGNED, RCycles, RCPU, offsetof(ARM, Cycles));
|
|
}
|
|
|
|
void Compiler::LoadReg(int reg, ARM64Reg nativeReg)
|
|
{
|
|
if (reg == 15)
|
|
MOVI2R(nativeReg, R15);
|
|
else
|
|
LDR(INDEX_UNSIGNED, nativeReg, RCPU, offsetof(ARM, R) + reg*4);
|
|
}
|
|
|
|
void Compiler::SaveReg(int reg, ARM64Reg nativeReg)
|
|
{
|
|
STR(INDEX_UNSIGNED, nativeReg, RCPU, offsetof(ARM, R) + reg*4);
|
|
}
|
|
|
|
void Compiler::LoadCPSR()
|
|
{
|
|
assert(!CPSRDirty);
|
|
LDR(INDEX_UNSIGNED, RCPSR, RCPU, offsetof(ARM, CPSR));
|
|
}
|
|
|
|
void Compiler::SaveCPSR(bool markClean)
|
|
{
|
|
if (CPSRDirty)
|
|
{
|
|
STR(INDEX_UNSIGNED, RCPSR, RCPU, offsetof(ARM, CPSR));
|
|
CPSRDirty = CPSRDirty && !markClean;
|
|
}
|
|
}
|
|
|
|
FixupBranch Compiler::CheckCondition(u32 cond)
|
|
{
|
|
if (cond >= 0x8)
|
|
{
|
|
LSR(W1, RCPSR, 28);
|
|
MOVI2R(W2, 1);
|
|
LSLV(W2, W2, W1);
|
|
ANDI2R(W2, W2, ARM::ConditionTable[cond], W3);
|
|
|
|
return CBZ(W2);
|
|
}
|
|
else
|
|
{
|
|
u8 bit = (28 + ((~(cond >> 1) & 1) << 1 | (cond >> 2 & 1) ^ (cond >> 1 & 1)));
|
|
|
|
if (cond & 1)
|
|
return TBNZ(RCPSR, bit);
|
|
else
|
|
return TBZ(RCPSR, bit);
|
|
}
|
|
}
|
|
|
|
#define F(x) &Compiler::A_Comp_##x
|
|
const Compiler::CompileFunc A_Comp[ARMInstrInfo::ak_Count] =
|
|
{
|
|
// AND
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// EOR
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// SUB
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// RSB
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// ADD
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// ADC
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// SBC
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// RSC
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// ORR
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// MOV
|
|
F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp),
|
|
F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp),
|
|
// BIC
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
|
// MVN
|
|
F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp),
|
|
F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp),
|
|
// TST
|
|
F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp),
|
|
// TEQ
|
|
F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp),
|
|
// CMP
|
|
F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp),
|
|
// CMN
|
|
F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp),
|
|
// Mul
|
|
F(Mul), F(Mul), F(Mul_Long), F(Mul_Long), F(Mul_Long), F(Mul_Long), F(Mul_Short), F(Mul_Short), F(Mul_Short), F(Mul_Short), F(Mul_Short),
|
|
// ARMv5 exclusives
|
|
F(Clz), NULL, NULL, NULL, NULL,
|
|
|
|
// STR
|
|
F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB),
|
|
// STRB
|
|
F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB),
|
|
// LDR
|
|
F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB),
|
|
// LDRB
|
|
F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB),
|
|
// STRH
|
|
F(MemHD), F(MemHD), F(MemHD), F(MemHD),
|
|
// LDRD
|
|
NULL, NULL, NULL, NULL,
|
|
// STRD
|
|
NULL, NULL, NULL, NULL,
|
|
// LDRH
|
|
F(MemHD), F(MemHD), F(MemHD), F(MemHD),
|
|
// LDRSB
|
|
F(MemHD), F(MemHD), F(MemHD), F(MemHD),
|
|
// LDRSH
|
|
F(MemHD), F(MemHD), F(MemHD), F(MemHD),
|
|
// Swap
|
|
NULL, NULL,
|
|
// LDM, STM
|
|
F(LDM_STM), F(LDM_STM),
|
|
// Branch
|
|
F(BranchImm), F(BranchImm), F(BranchImm), F(BranchXchangeReg), F(BranchXchangeReg),
|
|
// Special
|
|
NULL, F(MSR), F(MSR), F(MRS), NULL, NULL, NULL,
|
|
&Compiler::Nop
|
|
};
|
|
#undef F
|
|
#define F(x) &Compiler::T_Comp_##x
|
|
const Compiler::CompileFunc T_Comp[ARMInstrInfo::tk_Count] =
|
|
{
|
|
// Shift imm
|
|
F(ShiftImm), F(ShiftImm), F(ShiftImm),
|
|
// Add/sub tri operand
|
|
F(AddSub_), F(AddSub_), F(AddSub_), F(AddSub_),
|
|
// 8 bit imm
|
|
F(ALUImm8), F(ALUImm8), F(ALUImm8), F(ALUImm8),
|
|
// ALU
|
|
F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU),
|
|
F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU),
|
|
// ALU hi reg
|
|
F(ALU_HiReg), F(ALU_HiReg), F(ALU_HiReg),
|
|
// PC/SP relative ops
|
|
F(RelAddr), F(RelAddr), F(AddSP),
|
|
// LDR PC rel
|
|
F(LoadPCRel),
|
|
// LDR/STR reg offset
|
|
F(MemReg), F(MemReg), F(MemReg), F(MemReg),
|
|
// LDR/STR sign extended, half
|
|
F(MemRegHalf), F(MemRegHalf), F(MemRegHalf), F(MemRegHalf),
|
|
// LDR/STR imm offset
|
|
F(MemImm), F(MemImm), F(MemImm), F(MemImm),
|
|
// LDR/STR half imm offset
|
|
F(MemImmHalf), F(MemImmHalf),
|
|
// LDR/STR sp rel
|
|
F(MemSPRel), F(MemSPRel),
|
|
// PUSH/POP
|
|
F(PUSH_POP), F(PUSH_POP),
|
|
// LDMIA, STMIA
|
|
F(LDMIA_STMIA), F(LDMIA_STMIA),
|
|
// Branch
|
|
F(BCOND), F(BranchXchangeReg), F(BranchXchangeReg), F(B), F(BL_LONG_1), F(BL_LONG_2),
|
|
// Unk, SVC
|
|
NULL, NULL,
|
|
F(BL_Merged)
|
|
};
|
|
|
|
bool Compiler::CanCompile(bool thumb, u16 kind)
|
|
{
|
|
return (thumb ? T_Comp[kind] : A_Comp[kind]) != NULL;
|
|
}
|
|
|
|
void Compiler::Comp_BranchSpecialBehaviour(bool taken)
|
|
{
|
|
if (taken && CurInstr.BranchFlags & branch_IdleBranch)
|
|
{
|
|
MOVI2R(W0, 1);
|
|
STRB(INDEX_UNSIGNED, W0, RCPU, offsetof(ARM, IdleLoop));
|
|
}
|
|
|
|
if ((CurInstr.BranchFlags & branch_FollowCondNotTaken && taken)
|
|
|| (CurInstr.BranchFlags & branch_FollowCondTaken && !taken))
|
|
{
|
|
RegCache.PrepareExit();
|
|
|
|
if (ConstantCycles)
|
|
ADD(RCycles, RCycles, ConstantCycles);
|
|
QuickTailCall(X0, ARM_Ret);
|
|
}
|
|
}
|
|
|
|
JitBlockEntry Compiler::CompileBlock(ARM* cpu, bool thumb, FetchedInstr instrs[], int instrsCount, bool hasMemInstr)
|
|
{
|
|
if (JitMemMainSize - GetCodeOffset() < 1024 * 16)
|
|
{
|
|
Log(LogLevel::Debug, "JIT near memory full, resetting...\n");
|
|
NDS.JIT.ResetBlockCache();
|
|
}
|
|
if ((JitMemMainSize + JitMemSecondarySize) - OtherCodeRegion < 1024 * 8)
|
|
{
|
|
Log(LogLevel::Debug, "JIT far memory full, resetting...\n");
|
|
NDS.JIT.ResetBlockCache();
|
|
}
|
|
|
|
JitBlockEntry res = (JitBlockEntry)GetRXPtr();
|
|
|
|
Thumb = thumb;
|
|
Num = cpu->Num;
|
|
CurCPU = cpu;
|
|
ConstantCycles = 0;
|
|
RegCache = RegisterCache<Compiler, ARM64Reg>(this, instrs, instrsCount, true);
|
|
CPSRDirty = false;
|
|
|
|
if (hasMemInstr)
|
|
MOVP2R(RMemBase, Num == 0 ? NDS.JIT.Memory.FastMem9Start : NDS.JIT.Memory.FastMem7Start);
|
|
|
|
for (int i = 0; i < instrsCount; i++)
|
|
{
|
|
CurInstr = instrs[i];
|
|
R15 = CurInstr.Addr + (Thumb ? 4 : 8);
|
|
CodeRegion = R15 >> 24;
|
|
|
|
CompileFunc comp = Thumb
|
|
? T_Comp[CurInstr.Info.Kind]
|
|
: A_Comp[CurInstr.Info.Kind];
|
|
|
|
Exit = i == (instrsCount - 1) || (CurInstr.BranchFlags & branch_FollowCondNotTaken);
|
|
|
|
//printf("%x instr %x regs: r%x w%x n%x flags: %x %x %x\n", R15, CurInstr.Instr, CurInstr.Info.SrcRegs, CurInstr.Info.DstRegs, CurInstr.Info.ReadFlags, CurInstr.Info.NotStrictlyNeeded, CurInstr.Info.WriteFlags, CurInstr.SetFlags);
|
|
|
|
bool isConditional = Thumb ? CurInstr.Info.Kind == ARMInstrInfo::tk_BCOND : CurInstr.Cond() < 0xE;
|
|
if (comp == NULL || (CurInstr.BranchFlags & branch_FollowCondTaken) || (i == instrsCount - 1 && (!CurInstr.Info.Branches() || isConditional)))
|
|
{
|
|
MOVI2R(W0, R15);
|
|
STR(INDEX_UNSIGNED, W0, RCPU, offsetof(ARM, R[15]));
|
|
if (comp == NULL)
|
|
{
|
|
MOVI2R(W0, CurInstr.Instr);
|
|
STR(INDEX_UNSIGNED, W0, RCPU, offsetof(ARM, CurInstr));
|
|
}
|
|
if (Num == 0)
|
|
{
|
|
MOVI2R(W0, (s32)CurInstr.CodeCycles);
|
|
STR(INDEX_UNSIGNED, W0, RCPU, offsetof(ARM, CodeCycles));
|
|
}
|
|
}
|
|
|
|
if (comp == NULL)
|
|
{
|
|
SaveCycles();
|
|
SaveCPSR();
|
|
RegCache.Flush();
|
|
}
|
|
else
|
|
RegCache.Prepare(Thumb, i);
|
|
|
|
if (Thumb)
|
|
{
|
|
if (comp == NULL)
|
|
{
|
|
MOV(X0, RCPU);
|
|
QuickCallFunction(X1, InterpretTHUMB[CurInstr.Info.Kind]);
|
|
}
|
|
else
|
|
{
|
|
(this->*comp)();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
u32 cond = CurInstr.Cond();
|
|
if (CurInstr.Info.Kind == ARMInstrInfo::ak_BLX_IMM)
|
|
{
|
|
if (comp)
|
|
(this->*comp)();
|
|
else
|
|
{
|
|
MOV(X0, RCPU);
|
|
QuickCallFunction(X1, ARMInterpreter::A_BLX_IMM);
|
|
}
|
|
}
|
|
else if (cond == 0xF)
|
|
{
|
|
Comp_AddCycles_C();
|
|
}
|
|
else
|
|
{
|
|
IrregularCycles = comp == NULL;
|
|
|
|
FixupBranch skipExecute;
|
|
if (cond < 0xE)
|
|
skipExecute = CheckCondition(cond);
|
|
|
|
if (comp == NULL)
|
|
{
|
|
MOV(X0, RCPU);
|
|
QuickCallFunction(X1, InterpretARM[CurInstr.Info.Kind]);
|
|
}
|
|
else
|
|
{
|
|
(this->*comp)();
|
|
}
|
|
|
|
Comp_BranchSpecialBehaviour(true);
|
|
|
|
if (cond < 0xE)
|
|
{
|
|
if (IrregularCycles || (CurInstr.BranchFlags & branch_FollowCondTaken))
|
|
{
|
|
FixupBranch skipNop = B();
|
|
SetJumpTarget(skipExecute);
|
|
|
|
if (IrregularCycles)
|
|
Comp_AddCycles_C(true);
|
|
|
|
Comp_BranchSpecialBehaviour(false);
|
|
|
|
SetJumpTarget(skipNop);
|
|
}
|
|
else
|
|
{
|
|
SetJumpTarget(skipExecute);
|
|
}
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
if (comp == NULL)
|
|
{
|
|
LoadCycles();
|
|
LoadCPSR();
|
|
}
|
|
}
|
|
|
|
RegCache.Flush();
|
|
|
|
if (ConstantCycles)
|
|
ADD(RCycles, RCycles, ConstantCycles);
|
|
QuickTailCall(X0, ARM_Ret);
|
|
|
|
FlushIcache();
|
|
|
|
return res;
|
|
}
|
|
|
|
void Compiler::Reset()
|
|
{
|
|
LoadStorePatches.clear();
|
|
|
|
SetCodePtr(0);
|
|
OtherCodeRegion = JitMemMainSize;
|
|
|
|
const u32 brk_0 = 0xD4200000;
|
|
|
|
u8* const rw_ptr = GetWriteableRWPtr();
|
|
for (u32 i = 0; i < (JitMemMainSize + JitMemSecondarySize); i += sizeof(u32))
|
|
std::memcpy(rw_ptr + i, &brk_0, sizeof(u32));
|
|
}
|
|
|
|
void Compiler::Comp_AddCycles_C(bool forceNonConstant)
|
|
{
|
|
s32 cycles = Num ?
|
|
NDS.ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 1 : 3]
|
|
: ((R15 & 0x2) ? 0 : CurInstr.CodeCycles);
|
|
|
|
if (forceNonConstant)
|
|
ConstantCycles += cycles;
|
|
else
|
|
ADD(RCycles, RCycles, cycles);
|
|
}
|
|
|
|
void Compiler::Comp_AddCycles_CI(u32 numI)
|
|
{
|
|
IrregularCycles = true;
|
|
|
|
s32 cycles = (Num ?
|
|
NDS.ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2]
|
|
: ((R15 & 0x2) ? 0 : CurInstr.CodeCycles)) + numI;
|
|
|
|
if (Thumb || CurInstr.Cond() == 0xE)
|
|
ConstantCycles += cycles;
|
|
else
|
|
ADD(RCycles, RCycles, cycles);
|
|
}
|
|
|
|
void Compiler::Comp_AddCycles_CI(u32 c, ARM64Reg numI, ArithOption shift)
|
|
{
|
|
IrregularCycles = true;
|
|
|
|
s32 cycles = (Num ?
|
|
NDS.ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2]
|
|
: ((R15 & 0x2) ? 0 : CurInstr.CodeCycles)) + c;
|
|
|
|
ADD(RCycles, RCycles, cycles);
|
|
if (Thumb || CurInstr.Cond() >= 0xE)
|
|
ConstantCycles += cycles;
|
|
else
|
|
ADD(RCycles, RCycles, cycles);
|
|
}
|
|
|
|
void Compiler::Comp_AddCycles_CDI()
|
|
{
|
|
if (Num == 0)
|
|
Comp_AddCycles_CD();
|
|
else
|
|
{
|
|
IrregularCycles = true;
|
|
|
|
s32 cycles;
|
|
|
|
s32 numC = NDS.ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2];
|
|
s32 numD = CurInstr.DataCycles;
|
|
|
|
if ((CurInstr.DataRegion >> 24) == 0x02) // mainRAM
|
|
{
|
|
if (CodeRegion == 0x02)
|
|
cycles = numC + numD;
|
|
else
|
|
{
|
|
numC++;
|
|
cycles = std::max(numC + numD - 3, std::max(numC, numD));
|
|
}
|
|
}
|
|
else if (CodeRegion == 0x02)
|
|
{
|
|
numD++;
|
|
cycles = std::max(numC + numD - 3, std::max(numC, numD));
|
|
}
|
|
else
|
|
{
|
|
cycles = numC + numD + 1;
|
|
}
|
|
|
|
if (!Thumb && CurInstr.Cond() < 0xE)
|
|
ADD(RCycles, RCycles, cycles);
|
|
else
|
|
ConstantCycles += cycles;
|
|
}
|
|
}
|
|
|
|
void Compiler::Comp_AddCycles_CD()
|
|
{
|
|
u32 cycles = 0;
|
|
if (Num == 0)
|
|
{
|
|
s32 numC = (R15 & 0x2) ? 0 : CurInstr.CodeCycles;
|
|
s32 numD = CurInstr.DataCycles;
|
|
|
|
//if (DataRegion != CodeRegion)
|
|
cycles = std::max(numC + numD - 6, std::max(numC, numD));
|
|
|
|
IrregularCycles = cycles != numC;
|
|
}
|
|
else
|
|
{
|
|
s32 numC = NDS.ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2];
|
|
s32 numD = CurInstr.DataCycles;
|
|
|
|
if ((CurInstr.DataRegion >> 24) == 0x02)
|
|
{
|
|
if (CodeRegion == 0x02)
|
|
cycles += numC + numD;
|
|
else
|
|
cycles += std::max(numC + numD - 3, std::max(numC, numD));
|
|
}
|
|
else if (CodeRegion == 0x02)
|
|
{
|
|
cycles += std::max(numC + numD - 3, std::max(numC, numD));
|
|
}
|
|
else
|
|
{
|
|
cycles += numC + numD;
|
|
}
|
|
|
|
IrregularCycles = true;
|
|
}
|
|
|
|
if ((!Thumb && CurInstr.Cond() < 0xE) && IrregularCycles)
|
|
ADD(RCycles, RCycles, cycles);
|
|
else
|
|
ConstantCycles += cycles;
|
|
}
|
|
|
|
}
|