mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2024-06-06 07:08:54 -04:00
138 lines
3.4 KiB
C++
138 lines
3.4 KiB
C++
/*
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Copyright 2016-2023 melonDS team
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#ifndef ARMINTERPRETER_ALU_H
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#define ARMINTERPRETER_ALU_H
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namespace ARMInterpreter
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{
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#define A_PROTO_ALU_OP(x) \
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\
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void A_##x##_IMM(ARM* cpu); \
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void A_##x##_REG_LSL_IMM(ARM* cpu); \
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void A_##x##_REG_LSR_IMM(ARM* cpu); \
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void A_##x##_REG_ASR_IMM(ARM* cpu); \
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void A_##x##_REG_ROR_IMM(ARM* cpu); \
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void A_##x##_REG_LSL_REG(ARM* cpu); \
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void A_##x##_REG_LSR_REG(ARM* cpu); \
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void A_##x##_REG_ASR_REG(ARM* cpu); \
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void A_##x##_REG_ROR_REG(ARM* cpu); \
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void A_##x##_IMM_S(ARM* cpu); \
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void A_##x##_REG_LSL_IMM_S(ARM* cpu); \
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void A_##x##_REG_LSR_IMM_S(ARM* cpu); \
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void A_##x##_REG_ASR_IMM_S(ARM* cpu); \
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void A_##x##_REG_ROR_IMM_S(ARM* cpu); \
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void A_##x##_REG_LSL_REG_S(ARM* cpu); \
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void A_##x##_REG_LSR_REG_S(ARM* cpu); \
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void A_##x##_REG_ASR_REG_S(ARM* cpu); \
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void A_##x##_REG_ROR_REG_S(ARM* cpu);
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#define A_PROTO_ALU_TEST(x) \
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\
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void A_##x##_IMM(ARM* cpu); \
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void A_##x##_REG_LSL_IMM(ARM* cpu); \
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void A_##x##_REG_LSR_IMM(ARM* cpu); \
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void A_##x##_REG_ASR_IMM(ARM* cpu); \
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void A_##x##_REG_ROR_IMM(ARM* cpu); \
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void A_##x##_REG_LSL_REG(ARM* cpu); \
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void A_##x##_REG_LSR_REG(ARM* cpu); \
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void A_##x##_REG_ASR_REG(ARM* cpu); \
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void A_##x##_REG_ROR_REG(ARM* cpu);
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A_PROTO_ALU_OP(AND)
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A_PROTO_ALU_OP(EOR)
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A_PROTO_ALU_OP(SUB)
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A_PROTO_ALU_OP(RSB)
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A_PROTO_ALU_OP(ADD)
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A_PROTO_ALU_OP(ADC)
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A_PROTO_ALU_OP(SBC)
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A_PROTO_ALU_OP(RSC)
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A_PROTO_ALU_TEST(TST)
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A_PROTO_ALU_TEST(TEQ)
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A_PROTO_ALU_TEST(CMP)
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A_PROTO_ALU_TEST(CMN)
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A_PROTO_ALU_OP(ORR)
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A_PROTO_ALU_OP(MOV)
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A_PROTO_ALU_OP(BIC)
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A_PROTO_ALU_OP(MVN)
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void A_MOV_REG_LSL_IMM_DBG(ARM* cpu);
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void A_MUL(ARM* cpu);
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void A_MLA(ARM* cpu);
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void A_UMULL(ARM* cpu);
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void A_UMLAL(ARM* cpu);
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void A_SMULL(ARM* cpu);
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void A_SMLAL(ARM* cpu);
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void A_SMLAxy(ARM* cpu);
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void A_SMLAWy(ARM* cpu);
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void A_SMULxy(ARM* cpu);
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void A_SMULWy(ARM* cpu);
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void A_SMLALxy(ARM* cpu);
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void A_CLZ(ARM* cpu);
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void A_QADD(ARM* cpu);
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void A_QSUB(ARM* cpu);
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void A_QDADD(ARM* cpu);
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void A_QDSUB(ARM* cpu);
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void T_LSL_IMM(ARM* cpu);
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void T_LSR_IMM(ARM* cpu);
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void T_ASR_IMM(ARM* cpu);
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void T_ADD_REG_(ARM* cpu);
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void T_SUB_REG_(ARM* cpu);
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void T_ADD_IMM_(ARM* cpu);
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void T_SUB_IMM_(ARM* cpu);
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void T_MOV_IMM(ARM* cpu);
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void T_CMP_IMM(ARM* cpu);
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void T_ADD_IMM(ARM* cpu);
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void T_SUB_IMM(ARM* cpu);
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void T_AND_REG(ARM* cpu);
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void T_EOR_REG(ARM* cpu);
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void T_LSL_REG(ARM* cpu);
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void T_LSR_REG(ARM* cpu);
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void T_ASR_REG(ARM* cpu);
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void T_ADC_REG(ARM* cpu);
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void T_SBC_REG(ARM* cpu);
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void T_ROR_REG(ARM* cpu);
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void T_TST_REG(ARM* cpu);
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void T_NEG_REG(ARM* cpu);
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void T_CMP_REG(ARM* cpu);
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void T_CMN_REG(ARM* cpu);
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void T_ORR_REG(ARM* cpu);
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void T_MUL_REG(ARM* cpu);
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void T_BIC_REG(ARM* cpu);
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void T_MVN_REG(ARM* cpu);
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void T_ADD_HIREG(ARM* cpu);
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void T_CMP_HIREG(ARM* cpu);
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void T_MOV_HIREG(ARM* cpu);
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void T_ADD_PCREL(ARM* cpu);
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void T_ADD_SPREL(ARM* cpu);
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void T_ADD_SP(ARM* cpu);
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}
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#endif
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