mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2024-06-05 22:58:57 -04:00
301 lines
7.3 KiB
C++
301 lines
7.3 KiB
C++
/*
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Copyright 2016-2023 melonDS team
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include "ARMJIT_Compiler.h"
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using namespace Gen;
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namespace ARMJIT
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{
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template <typename T>
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int squeezePointer(T* ptr)
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{
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int truncated = (int)((u64)ptr);
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assert((T*)((u64)truncated) == ptr);
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return truncated;
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}
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void Compiler::Comp_JumpTo(u32 addr, bool forceNonConstantCycles)
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{
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// we can simplify constant branches by a lot
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IrregularCycles = true;
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u32 newPC;
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u32 cycles = 0;
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if (addr & 0x1 && !Thumb)
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{
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CPSRDirty = true;
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OR(32, R(RCPSR), Imm8(0x20));
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}
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else if (!(addr & 0x1) && Thumb)
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{
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CPSRDirty = true;
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AND(32, R(RCPSR), Imm32(~0x20));
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}
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if (Num == 0)
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{
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ARMv5* cpu9 = (ARMv5*)CurCPU;
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u32 regionCodeCycles = cpu9->MemTimings[addr >> 12][0];
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u32 compileTimeCodeCycles = cpu9->RegionCodeCycles;
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cpu9->RegionCodeCycles = regionCodeCycles;
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if (Exit)
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MOV(32, MDisp(RCPU, offsetof(ARMv5, RegionCodeCycles)), Imm32(regionCodeCycles));
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if (addr & 0x1)
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{
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addr &= ~0x1;
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newPC = addr+2;
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// two-opcodes-at-once fetch
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// doesn't matter if we put garbage in the MSbs there
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if (addr & 0x2)
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{
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cpu9->CodeRead32(addr-2, true);
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cycles += cpu9->CodeCycles;
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cpu9->CodeRead32(addr+2, false);
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cycles += CurCPU->CodeCycles;
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}
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else
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{
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cpu9->CodeRead32(addr, true);
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cycles += cpu9->CodeCycles;
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}
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}
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else
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{
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addr &= ~0x3;
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newPC = addr+4;
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cpu9->CodeRead32(addr, true);
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cycles += cpu9->CodeCycles;
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cpu9->CodeRead32(addr+4, false);
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cycles += cpu9->CodeCycles;
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}
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cpu9->RegionCodeCycles = compileTimeCodeCycles;
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}
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else
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{
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ARMv4* cpu7 = (ARMv4*)CurCPU;
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u32 codeRegion = addr >> 24;
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u32 codeCycles = addr >> 15; // cheato
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cpu7->CodeRegion = codeRegion;
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cpu7->CodeCycles = codeCycles;
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if (Exit)
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{
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MOV(32, MDisp(RCPU, offsetof(ARM, CodeRegion)), Imm32(codeRegion));
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MOV(32, MDisp(RCPU, offsetof(ARM, CodeCycles)), Imm32(codeCycles));
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}
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if (addr & 0x1)
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{
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addr &= ~0x1;
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newPC = addr+2;
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// this is necessary because ARM7 bios protection
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u32 compileTimePC = CurCPU->R[15];
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CurCPU->R[15] = newPC;
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cycles += NDS::ARM7MemTimings[codeCycles][0] + NDS::ARM7MemTimings[codeCycles][1];
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CurCPU->R[15] = compileTimePC;
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}
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else
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{
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addr &= ~0x3;
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newPC = addr+4;
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u32 compileTimePC = CurCPU->R[15];
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CurCPU->R[15] = newPC;
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cycles += NDS::ARM7MemTimings[codeCycles][2] + NDS::ARM7MemTimings[codeCycles][3];
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CurCPU->R[15] = compileTimePC;
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}
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cpu7->CodeRegion = R15 >> 24;
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cpu7->CodeCycles = addr >> 15;
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}
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if (Exit)
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MOV(32, MDisp(RCPU, offsetof(ARM, R[15])), Imm32(newPC));
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if ((Thumb || CurInstr.Cond() >= 0xE) && !forceNonConstantCycles)
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ConstantCycles += cycles;
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else
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), Imm8(cycles));
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}
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void ARMv4JumpToTrampoline(ARMv4* arm, u32 addr, bool restorecpsr)
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{
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arm->JumpTo(addr, restorecpsr);
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}
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void ARMv5JumpToTrampoline(ARMv5* arm, u32 addr, bool restorecpsr)
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{
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arm->JumpTo(addr, restorecpsr);
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}
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void Compiler::Comp_JumpTo(Gen::X64Reg addr, bool restoreCPSR)
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{
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IrregularCycles = true;
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bool cpsrDirty = CPSRDirty;
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SaveCPSR();
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PushRegs(restoreCPSR, true);
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MOV(64, R(ABI_PARAM1), R(RCPU));
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MOV(32, R(ABI_PARAM2), R(addr));
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if (!restoreCPSR)
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XOR(32, R(ABI_PARAM3), R(ABI_PARAM3));
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else
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MOV(32, R(ABI_PARAM3), Imm32(true)); // what a waste
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if (Num == 0)
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CALL((void*)&ARMv5JumpToTrampoline);
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else
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CALL((void*)&ARMv4JumpToTrampoline);
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PopRegs(restoreCPSR, true);
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LoadCPSR();
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// in case this instruction is skipped
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if (CurInstr.Cond() < 0xE)
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CPSRDirty = cpsrDirty;
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}
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void Compiler::A_Comp_BranchImm()
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{
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int op = (CurInstr.Instr >> 24) & 1;
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s32 offset = (s32)(CurInstr.Instr << 8) >> 6;
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u32 target = R15 + offset;
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bool link = op;
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if (CurInstr.Cond() == 0xF) // BLX_imm
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{
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target += (op << 1) + 1;
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link = true;
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}
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if (link)
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MOV(32, MapReg(14), Imm32(R15 - 4));
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Comp_JumpTo(target);
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}
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void Compiler::A_Comp_BranchXchangeReg()
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{
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OpArg rn = MapReg(CurInstr.A_Reg(0));
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MOV(32, R(RSCRATCH), rn);
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if ((CurInstr.Instr & 0xF0) == 0x30) // BLX_reg
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MOV(32, MapReg(14), Imm32(R15 - 4));
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Comp_JumpTo(RSCRATCH);
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}
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void Compiler::T_Comp_BCOND()
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{
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u32 cond = (CurInstr.Instr >> 8) & 0xF;
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FixupBranch skipExecute = CheckCondition(cond);
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s32 offset = (s32)(CurInstr.Instr << 24) >> 23;
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Comp_JumpTo(R15 + offset + 1, true);
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Comp_SpecialBranchBehaviour(true);
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FixupBranch skipFailed = J();
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SetJumpTarget(skipExecute);
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Comp_SpecialBranchBehaviour(false);
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Comp_AddCycles_C(true);
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SetJumpTarget(skipFailed);
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}
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void Compiler::T_Comp_B()
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{
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s32 offset = (s32)((CurInstr.Instr & 0x7FF) << 21) >> 20;
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Comp_JumpTo(R15 + offset + 1);
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}
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void Compiler::T_Comp_BranchXchangeReg()
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{
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bool link = CurInstr.Instr & (1 << 7);
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if (link)
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{
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if (Num == 1)
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{
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Log(LogLevel::Warn, "BLX unsupported on ARM7!!!\n");
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return;
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}
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MOV(32, R(RSCRATCH), MapReg(CurInstr.A_Reg(3)));
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MOV(32, MapReg(14), Imm32(R15 - 1));
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Comp_JumpTo(RSCRATCH);
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}
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else
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{
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OpArg rn = MapReg(CurInstr.A_Reg(3));
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Comp_JumpTo(rn.GetSimpleReg());
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}
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}
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void Compiler::T_Comp_BL_LONG_1()
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{
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s32 offset = (s32)((CurInstr.Instr & 0x7FF) << 21) >> 9;
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MOV(32, MapReg(14), Imm32(R15 + offset));
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Comp_AddCycles_C();
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}
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void Compiler::T_Comp_BL_LONG_2()
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{
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OpArg lr = MapReg(14);
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s32 offset = (CurInstr.Instr & 0x7FF) << 1;
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LEA(32, RSCRATCH, MDisp(lr.GetSimpleReg(), offset));
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MOV(32, lr, Imm32((R15 - 2) | 1));
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if (Num == 1 || CurInstr.Instr & (1 << 12))
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OR(32, R(RSCRATCH), Imm8(1));
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Comp_JumpTo(RSCRATCH);
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}
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void Compiler::T_Comp_BL_Merged()
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{
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Comp_AddCycles_C();
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R15 += 2;
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u32 upperPart = CurInstr.Instr >> 16;
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u32 target = (R15 - 2) + ((s32)((CurInstr.Instr & 0x7FF) << 21) >> 9);
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target += (upperPart & 0x7FF) << 1;
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if (Num == 1 || upperPart & (1 << 12))
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target |= 1;
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MOV(32, MapReg(14), Imm32((R15 - 2) | 1));
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Comp_JumpTo(target);
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}
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}
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