added 74HC04 inverter

corrected controller implementation
This commit is contained in:
Icer 2022-04-13 14:45:33 -07:00
parent 35e622c6a1
commit 6acddfb97f
6 changed files with 177 additions and 70 deletions

View file

@ -316,7 +316,7 @@ HANDLE_EVENT(scrollWheel)
[self updateControllers];
// [self updateControllers];
// ImGuiSupport_NewFrame();

78
data/system-def/74HC04.js Normal file
View file

@ -0,0 +1,78 @@
/*
*/
var module = {
name: "74HC04",
description: "Simple logic inverter",
pins : [
[ 1, '1A' ],
[ 2, '1Y' ],
[ 3, '2A' ],
[ 4, '2Y' ],
[ 5, '3A' ],
[ 6, '3Y' ],
[ 7, 'vss' ],
[14, 'vcc' ],
[13, '6A' ],
[12, '6Y' ],
[11, '5A' ],
[10, '5Y' ],
[ 9, '4A' ],
[ 8, '4Y' ],
],
nodenames :
{
vcc: 1,
vss: 2,
'1A': 11,
'2A': 12,
'3A': 13,
'4A': 14,
'5A': 15,
'6A': 16,
'1Y': 21,
'2Y': 22,
'3Y': 23,
'4Y': 24,
'5Y': 25,
'6Y': 26,
},
transdefs:
[
['t', '1A', '1Y', 2 ],
['t', '2A', '2Y', 2 ],
['t', '3A', '3Y', 2 ],
['t', '4A', '4Y', 2 ],
['t', '5A', '5Y', 2 ],
['t', '6A', '6Y', 2 ],
],
segdefs: [
['1Y' , '+', 0],
['2Y' , '+', 0],
['3Y' , '+', 0],
['4Y' , '+', 0],
['5Y' , '+', 0],
['6Y' , '+', 0],
]
};

View file

@ -17,12 +17,13 @@ modules: [
[ "u2", "74LS373", 0],
[ "u3", "74LS139", 0],
[ "u4", "SRAM2K", 0],
[ "u7", "74LS368", 0],
[ "u8", "74LS368", 0],
[ "u7", "74LS368", 0], // logic inverter
[ "u8", "74LS368", 0], // logic inverter
[ "u9", "74HC04", 0], // simple logic inverter
[ "u10", "nes-cic1", 0],
[ "port0", "nes-pad", 0],
[ "port1", "nes-pad", 0],
[ "cart.edge", "nes-cart72", 0],
[ "port0", "nes-pad", 0], // left controller port
[ "port1", "nes-pad", 0], // right controller port
[ "cart.edge", "nes-cart72", 0], // cartridge interface
],
@ -154,10 +155,9 @@ connections:
// wire up u7 inverter for ppu a13
[ "vss", "u7./2OE" ],
[ "ppu.ab13", "u7.2A2" ],
[ "u7./2Y2", "cart.edge.ppu_/a13" ],
// wire up inverter for ppu a13
[ "ppu.ab13", "u9.3A" ],
[ "u9.3Y", "cart.edge.ppu_/a13" ],
// data <-> VRAM
@ -172,39 +172,48 @@ connections:
// controller ports
//
[ "cpu.clk0", "u8.#2" ],
[ "cpu.clk0", "u7.#6" ],
[ "cpu.joy1", "u7.#1" ],
//[ "cpu.joy1", "u7.#15" ],
// left controller
[ "cpu.out0", "port0.out" ],
[ "u7./1OE", "cpu.joy1" ],
[ "u7./2OE", "cpu.joy1" ],
[ "cpu.joy2", "u8.#1" ],
[ "cpu.joy2", "u8.#15" ],
[ "u7.1A1", "cpu.clk0" ],
[ "u7.1A2", "port0.d0" ],
[ "u7.1A3", "vcc" ],
[ "u7.1A4", "vss" ],
[ "u7.2A1", "vss" ],
[ "u7.2A2", "vss" ],
[ "u7./1Y1", "port0.clk" ],
[ "u7./1Y2", "cpu.db0" ],
[ "u7./1Y3", "cpu.db1" ],
[ "u7./1Y4", "cpu.db2" ],
[ "u7./2Y1", "cpu.db3" ],
[ "u7./2Y2", "cpu.db4" ],
[ "u7.#3", "cpu.db0" ],
[ "u7.#5", "cpu.db1" ],
[ "u7.#9", "cpu.db2" ],
// right controller
[ "cpu.out0", "port1.out" ],
[ "u8./1OE", "cpu.joy2" ],
[ "u8./2OE", "cpu.joy2" ],
[ "u8.#13", "cpu.db0" ],
[ "u8.#5", "cpu.db1" ],
[ "u8.#11", "cpu.db2" ],
[ "u8.#7", "cpu.db3" ],
[ "u8.#9", "cpu.db4" ],
[ "port0.out", "cpu.out0" ],
[ "port0.clk", "u7.#7" ],
[ "port0.d0", "u7.#2" ],
[ "port1.out", "cpu.out0" ],
[ "port1.clk", "u7.#7" ],
[ "port1.d0", "u7.#4" ],
// [ "port0.d0", "vcc" ],
// [ "port1.d0", "vcc" ],
[ "u8.1A1", "cpu.clk0" ],
[ "u8.1A2", "port1.d0" ],
[ "u8.1A3", "vcc" ],
[ "u8.1A4", "vss" ],
[ "u8.2A1", "vss" ],
[ "u8.2A2", "vss" ],
[ "u8./1Y1", "port1.clk" ],
[ "u8./1Y2", "cpu.db0" ],
[ "u8./1Y3", "cpu.db1" ],
[ "u8./1Y4", "cpu.db2" ],
[ "u8./2Y1", "cpu.db3" ],
[ "u8./2Y2", "cpu.db4" ],
// wire from cart to VRAM A10 and CS lines
[ "cart.edge.ciram_a10", "u4.a10" ],

View file

@ -17,22 +17,13 @@ name: "nes-pad",
description: "NES D-pad",
pins: [
[ 1, 'vcc' ],
[ 2, 'd3' ],
[ 3, 'd4' ],
[ 4, 'd0' ],
[ 5, 'out' ],
[ 6, 'clk' ],
[ 7, 'vss' ],
[ 8, 'buttons0' ],
[ 9, 'buttons1' ],
[10, 'buttons2' ],
[11, 'buttons3' ],
[12, 'buttons4' ],
[13, 'buttons5' ],
[14, 'buttons6' ],
[15, 'buttons7' ]
[ 1, 'vss' ],
[ 2, 'oe' ],
[ 3, 'out' ],
[ 4, 'd0' ],
[ 5, 'vcc' ],
[ 6, 'd3' ],
[ 7, 'd4' ],
],
modules: [
@ -45,6 +36,10 @@ connections: [
["shift.CLK", "clk"],
["shift.PL", "out"],
["shift.DS", "vss"],
["d1", "vcc"],
["d2", "vss"],
["d3", "vss"],
["d4", "vss"],
],
@ -55,10 +50,15 @@ nodenames :
out:3,
clk:4,
oe:4,
d0:5,
d3:6,
d4:7,
d1:6,
d2:7,
d3:8,
d4:9,
'buttons0': 10,
'buttons1': 11,
'buttons2': 12,

View file

@ -456,9 +456,7 @@ public:
void onGui()
void onGuiController(int &pad)
{
static const char *s_ButtonNames[8] =
{
@ -472,6 +470,23 @@ public:
"Right"
};
for (int i=0; i < 8; i++)
{
int bit = (0x80>>i); // flip bit ordering
bool isdown = (pad & bit);
if (ToggleButton(s_ButtonNames[i], &isdown))
{
pad ^= bit;
}
ImGui::SameLine();
}
}
void onGui()
{
int halfCycle = getTime();
int deltaCycle = halfCycle - _prevhalfcycle;
@ -491,18 +506,20 @@ public:
// ImGui::SameLine();
for (int i=0; i < 8; i++)
{
bool isdown = (_pad0 & (1<<i));
if (ToggleButton(s_ButtonNames[i], &isdown))
{
_pad0 ^= (1<<i);
}
ImGui::SameLine();
}
ToggleButton("ClearOnRead", &_pad_clear);
ImGui::PushID("#pad0");
ImGui::Text("pad0:");
ImGui::SameLine();
onGuiController(_pad0);
ToggleButton("ClearOnRead", &_pad_clear);
ImGui::PopID();
ImGui::PushID("#pad1");
ImGui::Text("pad1:");
ImGui::SameLine();
onGuiController(_pad1);
ImGui::PopID();
ImGui::NewLine();

View file

@ -524,6 +524,9 @@ system_state_ptr system_state::Create(std::string system_def_dir, std::string st
// _tracedColumns = "port0.shift.CLK,port0.shift.PL,cpu.out1,port0.d0,port0.buttons[],port0.shift.d[],port0.shift.q7,port0.shift.q6,port0.shift.q5,port0.shift.L0.clk";
// _tracedColumns = "cpu.joy1,cpu.joy2,cpu.out[],-,cpu.clk0,port0.buttons[],cpu.db[4:0]";
if (!_tracedColumns.empty())
{
auto log = state->add_handler<handler_log>("");