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Merge pull request #739 from loganmc10/cause_bi

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IP0 and IP1 CAUSE bits are writeable
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bsmiles32 2020-03-29 14:21:20 +02:00 committed by GitHub
parent fedf950be7 34a1b62314
commit 4222bc20f6
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GPG key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 6 deletions
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8
src/device/r4300/mips_instructions.def
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@ -1284,12 +1284,8 @@ DECLARE_INSTRUCTION(MTC0)
ADD_TO_PC(-1);
break;
case CP0_CAUSE_REG:
if (rrt32 != 0)
{
DebugMessage(M64MSG_ERROR, "MTC0 instruction trying to write Cause register with non-0 value");
*r4300_stop(r4300) = 1;
}
else { cp0_regs[CP0_CAUSE_REG] = rrt32; }
cp0_regs[CP0_CAUSE_REG] &= ~(CP0_CAUSE_IP0 | CP0_CAUSE_IP1);
cp0_regs[CP0_CAUSE_REG] |= rrt32 & (CP0_CAUSE_IP0 | CP0_CAUSE_IP1);
break;
case CP0_EPC_REG:
cp0_regs[CP0_EPC_REG] = rrt32;