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Rewrote overclock implementation

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Rename enable_overclock to count_per_op_denom_pot
Renamed cfg option
This commit is contained in:
carnivoroussociety 2020-12-08 05:42:03 +00:00 committed by GitHub
parent 245d917fa9
commit cf615aa446
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GPG key ID: 4AEE18F83AFDEB23
14 changed files with 44 additions and 74 deletions
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4
doc/emuwiki-api-doc/Mupen64Plus-Core-Parameters.mediawiki
View file

@ -59,9 +59,9 @@ These are standard parameters which are used by the Mupen64Plus Core library. T
|M64TYPE_INT
|Force number of cycles per emulated instruction when set greater than 0.
|-
|EnableOverclock
|CountPerOpDenomPot
|M64TYPE_INT
|Override cycle calculation with reduced count factor (overclock) when set greater than 0.
|Reduce number of cycles per update by power of two when set greater than 0 (overclock).
|-
|}

4
doc/emuwiki-api-doc/Mupen64Plus-v2.0-Netplay-API.mediawiki
View file

@ -85,7 +85,7 @@ The server is responsible for maintaining healthy buffers and also for detecting
** 25 bytes
** byte[0] = 3
** byte[1-4] = count_per_op
** byte[5-8] = enable_overclock
** byte[5-8] = count_per_op_denom_pot
** byte[9-12] = disable_extra_mem
** byte[13-16] = si_dma_duration
** byte[17-20] = emumode
@ -99,7 +99,7 @@ The server is responsible for maintaining healthy buffers and also for detecting
** Server responds with this data right after the above request
** 24 bytes
** byte[0-3] = count_per_op
** byte[4-7] = enable_overclock
** byte[4-7] = count_per_op_denom_pot
** byte[8-11] = disable_extra_mem
** byte[12-15] = si_dma_duration
** byte[16-19] = emumode

4
src/device/device.c
View file

@ -83,7 +83,7 @@ void init_device(struct device* dev,
/* r4300 */
unsigned int emumode,
unsigned int count_per_op,
unsigned int enable_overclock,
unsigned int count_per_op_denom_pot,
int no_compiled_jump,
int randomize_interrupt,
uint32_t start_address,
@ -178,7 +178,7 @@ void init_device(struct device* dev,
init_rdram(&dev->rdram, mem_base_u32(base, MM_RDRAM_DRAM), dram_size, &dev->r4300);
init_r4300(&dev->r4300, &dev->mem, &dev->mi, &dev->rdram, interrupt_handlers,
emumode, count_per_op, enable_overclock, no_compiled_jump, randomize_interrupt, start_address);
emumode, count_per_op, count_per_op_denom_pot, no_compiled_jump, randomize_interrupt, start_address);
init_rdp(&dev->dp, &dev->sp, &dev->mi, &dev->mem, &dev->rdram, &dev->r4300);
init_rsp(&dev->sp, mem_base_u32(base, MM_RSP_MEM), &dev->mi, &dev->dp, &dev->ri);
init_ai(&dev->ai, &dev->mi, &dev->ri, &dev->vi, aout, iaout);

2
src/device/device.h
View file

@ -118,7 +118,7 @@ void init_device(struct device* dev,
/* r4300 */
unsigned int emumode,
unsigned int count_per_op,
unsigned int enable_overclock,
unsigned int count_per_op_denom_pot,
int no_compiled_jump,
int randomize_interrupt,
uint32_t start_address,

19
src/device/r4300/cp0.c
View file

@ -36,10 +36,10 @@
#endif
/* global functions */
void init_cp0(struct cp0* cp0, unsigned int count_per_op, unsigned int enable_overclock, struct new_dynarec_hot_state* new_dynarec_hot_state, const struct interrupt_handler* interrupt_handlers)
void init_cp0(struct cp0* cp0, unsigned int count_per_op, unsigned int count_per_op_denom_pot, struct new_dynarec_hot_state* new_dynarec_hot_state, const struct interrupt_handler* interrupt_handlers)
{
cp0->count_per_op = count_per_op;
cp0->enable_overclock = enable_overclock;
cp0->count_per_op_denom_pot = count_per_op_denom_pot;
#ifdef NEW_DYNAREC
cp0->new_dynarec_hot_state = new_dynarec_hot_state;
#endif
@ -139,17 +139,10 @@ void cp0_update_count(struct r4300_core* r4300)
if (r4300->emumode != EMUMODE_DYNAREC)
{
#endif
uint32_t count;
if (!cp0->enable_overclock) {
count = ((*r4300_pc(r4300) - cp0->last_addr) >> 2) * cp0->count_per_op;
}
else {
uint32_t oc_factor = r4300->cp0.enable_overclock;
count = ((*r4300_pc(r4300) - cp0->last_addr) >> 2);
while (oc_factor) {
count -= count >> 1;
oc_factor--;
}
uint32_t count = ((*r4300_pc(r4300) - cp0->last_addr) >> 2) * cp0->count_per_op;
if (r4300->cp0.count_per_op_denom_pot) {
count += (1 << r4300->cp0.count_per_op_denom_pot) - 1;
count >>= r4300->cp0.count_per_op_denom_pot;
}
cp0_regs[CP0_COUNT_REG] += count;
*r4300_cp0_cycle_count(cp0) += count;

4
src/device/r4300/cp0.h
View file

@ -200,7 +200,7 @@ struct cp0
uint32_t last_addr;
unsigned int count_per_op;
unsigned int enable_overclock;
unsigned int count_per_op_denom_pot;
struct tlb tlb;
};
@ -215,7 +215,7 @@ struct cp0
offsetof(struct new_dynarec_hot_state, cp0_regs))
#endif
void init_cp0(struct cp0* cp0, unsigned int count_per_op, unsigned int enable_overclock, struct new_dynarec_hot_state* new_dynarec_hot_state, const struct interrupt_handler* interrupt_handlers);
void init_cp0(struct cp0* cp0, unsigned int count_per_op, unsigned int count_per_op_denom_pot, struct new_dynarec_hot_state* new_dynarec_hot_state, const struct interrupt_handler* interrupt_handlers);
void poweron_cp0(struct cp0* cp0);
uint32_t* r4300_cp0_regs(struct cp0* cp0);

13
src/device/r4300/new_dynarec/new_dynarec.c
View file

@ -5668,16 +5668,11 @@ static void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int i
emit_jmp(0);
}
else if(*adj==0||invert) {
if(!g_dev.r4300.cp0.enable_overclock) {
emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
} else {
uint32_t oc_factor = g_dev.r4300.cp0.enable_overclock;
while (oc_factor) {
count -= count >> 1;
oc_factor--;
}
emit_addimm_and_set_flags((count+2),HOST_CCREG);
if(g_dev.r4300.cp0.count_per_op_denom_pot) {
count += (1 << g_dev.r4300.cp0.count_per_op_denom_pot) - 1;
count >>= g_dev.r4300.cp0.count_per_op_denom_pot;
}
emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
jaddr=(intptr_t)out;
emit_jns(0);
}

4
src/device/r4300/r4300_core.c
View file

@ -41,7 +41,7 @@
#include <time.h>
void init_r4300(struct r4300_core* r4300, struct memory* mem, struct mi_controller* mi, struct rdram* rdram, const struct interrupt_handler* interrupt_handlers,
unsigned int emumode, unsigned int count_per_op, unsigned int enable_overclock, int no_compiled_jump, int randomize_interrupt, uint32_t start_address)
unsigned int emumode, unsigned int count_per_op, unsigned int count_per_op_denom_pot, int no_compiled_jump, int randomize_interrupt, uint32_t start_address)
{
struct new_dynarec_hot_state* new_dynarec_hot_state =
#ifdef NEW_DYNAREC
@ -51,7 +51,7 @@ void init_r4300(struct r4300_core* r4300, struct memory* mem, struct mi_controll
#endif
r4300->emumode = emumode;
init_cp0(&r4300->cp0, count_per_op, enable_overclock, new_dynarec_hot_state, interrupt_handlers);
init_cp0(&r4300->cp0, count_per_op, count_per_op_denom_pot, new_dynarec_hot_state, interrupt_handlers);
init_cp1(&r4300->cp1, new_dynarec_hot_state);
#ifndef NEW_DYNAREC

2
src/device/r4300/r4300_core.h
View file

@ -211,7 +211,7 @@ struct r4300_core
offsetof(struct new_dynarec_hot_state, regs))
#endif
void init_r4300(struct r4300_core* r4300, struct memory* mem, struct mi_controller* mi, struct rdram* rdram, const struct interrupt_handler* interrupt_handlers, unsigned int emumode, unsigned int count_per_op, unsigned int enable_overclock, int no_compiled_jump, int randomize_interrupt, uint32_t start_address);
void init_r4300(struct r4300_core* r4300, struct memory* mem, struct mi_controller* mi, struct rdram* rdram, const struct interrupt_handler* interrupt_handlers, unsigned int emumode, unsigned int count_per_op, unsigned int count_per_op_denom_pot, int no_compiled_jump, int randomize_interrupt, uint32_t start_address);
void poweron_r4300(struct r4300_core* r4300);
void run_r4300(struct r4300_core* r4300);

19
src/device/r4300/x86/dynarec.c
View file

@ -126,21 +126,12 @@ static void gencp0_update_count(struct r4300_core* r4300, unsigned int addr)
mov_reg32_imm32(EAX, addr);
sub_reg32_m32(EAX, (unsigned int*)(&r4300->cp0.last_addr));
shr_reg32_imm8(EAX, 2);
if (!r4300->cp0.enable_overclock)
mov_reg32_m32(EDX, &r4300->cp0.count_per_op);
mul_reg32(EDX);
if (r4300->cp0.count_per_op_denom_pot)
{
mov_reg32_m32(EDX, &r4300->cp0.count_per_op);
mul_reg32(EDX);
}
else
{
unsigned int oc_factor = r4300->cp0.enable_overclock;
while (oc_factor)
{
mov_reg32_reg32(EDX, EAX);
shr_reg32_imm8(EDX, 1);
sub_reg32_reg32(EAX, EDX);
oc_factor--;
}
add_reg32_imm32(EAX, (1 << g_dev.r4300.cp0.count_per_op_denom_pot) - 1);
shr_reg32_imm8(EAX, g_dev.r4300.cp0.count_per_op_denom_pot);
}
add_m32_reg32((unsigned int*)(&r4300_cp0_regs(&r4300->cp0)[CP0_COUNT_REG]), EAX);
add_m32_reg32((unsigned int*)r4300_cp0_cycle_count(&r4300->cp0), EAX);

19
src/device/r4300/x86_64/dynarec.c
View file

@ -137,21 +137,12 @@ static void gencp0_update_count(struct r4300_core* r4300, unsigned int addr)
mov_reg32_imm32(EAX, addr);
sub_xreg32_m32rel(EAX, (unsigned int*)(&r4300->cp0.last_addr));
shr_reg32_imm8(EAX, 2);
if (!r4300->cp0.enable_overclock)
mov_xreg32_m32rel(EDX, (void*)&r4300->cp0.count_per_op);
mul_reg32(EDX);
if (r4300->cp0.count_per_op_denom_pot)
{
mov_xreg32_m32rel(EDX, (void*)&r4300->cp0.count_per_op);
mul_reg32(EDX);
}
else
{
unsigned int oc_factor = r4300->cp0.enable_overclock;
while (oc_factor)
{
mov_reg32_reg32(EDX, EAX);
shr_reg32_imm8(EDX, 1);
sub_reg32_reg32(EAX, EDX);
oc_factor--;
}
add_reg32_imm32(EAX, (1 << g_dev.r4300.cp0.count_per_op_denom_pot) - 1);
shr_reg32_imm8(EAX, g_dev.r4300.cp0.count_per_op_denom_pot);
}
add_m32rel_xreg32((unsigned int*)(&r4300_cp0_regs(&r4300->cp0)[CP0_COUNT_REG]), EAX);
add_m32rel_xreg32((unsigned int*)(r4300_cp0_cycle_count(&r4300->cp0)), EAX);

14
src/main/main.c
View file

@ -308,7 +308,7 @@ int main_set_core_defaults(void)
ConfigSetDefaultString(g_CoreConfig, "SaveSRAMPath", "", "Path to directory where SRAM/EEPROM data (in-game saves) are stored. If this is blank, the default value of ${UserDataPath}/save will be used");
ConfigSetDefaultString(g_CoreConfig, "SharedDataPath", "", "Path to a directory to search when looking for shared data files");
ConfigSetDefaultInt(g_CoreConfig, "CountPerOp", 0, "Force number of cycles per emulated instruction");
ConfigSetDefaultInt(g_CoreConfig, "EnableOverclock", 0, "Override cycle calculation with reduced count factor (overclock)");
ConfigSetDefaultInt(g_CoreConfig, "CountPerOpDenomPot", 0, "Reduce number of cycles per update by power of two when set greater than 0 (overclock).");
ConfigSetDefaultBool(g_CoreConfig, "RandomizeInterrupt", 1, "Randomize PI/SI Interrupt Timing");
ConfigSetDefaultInt(g_CoreConfig, "SiDmaDuration", -1, "Duration of SI DMA (-1: use per game settings)");
ConfigSetDefaultString(g_CoreConfig, "GbCameraVideoCaptureBackend1", DEFAULT_VIDEO_CAPTURE_BACKEND, "Gameboy Camera Video Capture backend");
@ -1305,7 +1305,7 @@ m64p_error main_run(void)
size_t i, k;
size_t rdram_size;
uint32_t count_per_op;
uint32_t enable_overclock;
uint32_t count_per_op_denom_pot;
uint32_t emumode;
uint32_t disable_extra_mem;
int32_t si_dma_duration;
@ -1340,7 +1340,7 @@ m64p_error main_run(void)
//We disable any randomness for netplay
randomize_interrupt = !netplay_is_init() ? ConfigGetParamBool(g_CoreConfig, "RandomizeInterrupt") : 0;
count_per_op = ConfigGetParamInt(g_CoreConfig, "CountPerOp");
enable_overclock = ConfigGetParamInt(g_CoreConfig, "EnableOverclock");
count_per_op_denom_pot = ConfigGetParamInt(g_CoreConfig, "CountPerOpDenomPot");
if (ROM_PARAMS.disableextramem)
disable_extra_mem = ROM_PARAMS.disableextramem;
@ -1353,15 +1353,15 @@ m64p_error main_run(void)
if (count_per_op <= 0)
count_per_op = ROM_PARAMS.countperop;
if (enable_overclock > 50)
enable_overclock = 50;
if (count_per_op_denom_pot > 50)
count_per_op_denom_pot = 50;
si_dma_duration = ConfigGetParamInt(g_CoreConfig, "SiDmaDuration");
if (si_dma_duration < 0)
si_dma_duration = ROM_PARAMS.sidmaduration;
//During netplay, player 1 is the source of truth for these settings
netplay_sync_settings(&count_per_op, &enable_overclock, &disable_extra_mem, &si_dma_duration, &emumode, &no_compiled_jump);
netplay_sync_settings(&count_per_op, &count_per_op_denom_pot, &disable_extra_mem, &si_dma_duration, &emumode, &no_compiled_jump);
cheat_add_hacks(&g_cheat_ctx, ROM_PARAMS.cheats);
@ -1579,7 +1579,7 @@ m64p_error main_run(void)
g_mem_base,
emumode,
count_per_op,
enable_overclock,
count_per_op_denom_pot,
no_compiled_jump,
randomize_interrupt,
g_start_address,

6
src/main/netplay.c
View file

@ -483,7 +483,7 @@ file_status_t netplay_read_storage(const char *filename, void *data, size_t size
return ret;
}
void netplay_sync_settings(uint32_t *count_per_op, uint32_t *enable_overclock, uint32_t *disable_extra_mem, int32_t *si_dma_duration, uint32_t *emumode, int32_t *no_compiled_jump)
void netplay_sync_settings(uint32_t *count_per_op, uint32_t *count_per_op_denom_pot, uint32_t *disable_extra_mem, int32_t *si_dma_duration, uint32_t *emumode, int32_t *no_compiled_jump)
{
if (!netplay_is_init())
return;
@ -495,7 +495,7 @@ void netplay_sync_settings(uint32_t *count_per_op, uint32_t *enable_overclock, u
request = TCP_SEND_SETTINGS;
memcpy(&output_data[0], &request, 1);
SDLNet_Write32(*count_per_op, &output_data[1]);
SDLNet_Write32(*enable_overclock, &output_data[5]);
SDLNet_Write32(*count_per_op_denom_pot, &output_data[5]);
SDLNet_Write32(*disable_extra_mem, &output_data[9]);
SDLNet_Write32(*si_dma_duration, &output_data[13]);
SDLNet_Write32(*emumode, &output_data[17]);
@ -511,7 +511,7 @@ void netplay_sync_settings(uint32_t *count_per_op, uint32_t *enable_overclock, u
while (recv < 24)
recv += SDLNet_TCP_Recv(l_tcpSocket, &output_data[recv], 24 - recv);
*count_per_op = SDLNet_Read32(&output_data[0]);
*enable_overclock = SDLNet_Read32(&output_data[4]);
*count_per_op_denom_pot = SDLNet_Read32(&output_data[4]);
*disable_extra_mem = SDLNet_Read32(&output_data[8]);
*si_dma_duration = SDLNet_Read32(&output_data[12]);
*emumode = SDLNet_Read32(&output_data[16]);

4
src/main/netplay.h
View file

@ -47,7 +47,7 @@ void netplay_set_controller(uint8_t player);
int netplay_is_init();
int netplay_get_controller(uint8_t player);
file_status_t netplay_read_storage(const char *filename, void *data, size_t size);
void netplay_sync_settings(uint32_t *count_per_op, uint32_t *enable_overclock, uint32_t *disable_extra_mem, int32_t *si_dma_duration, uint32_t *emumode, int32_t *no_compiled_jump);
void netplay_sync_settings(uint32_t *count_per_op, uint32_t *count_per_op_denom_pot, uint32_t *disable_extra_mem, int32_t *si_dma_duration, uint32_t *emumode, int32_t *no_compiled_jump);
void netplay_check_sync(struct cp0* cp0);
int netplay_next_controller();
void netplay_read_registration(struct controller_input_compat* cin_compats);
@ -97,7 +97,7 @@ static osal_inline file_status_t netplay_read_storage(const char *filename, void
return 0;
}
static osal_inline void netplay_sync_settings(uint32_t *count_per_op, uint32_t *enable_overclock, uint32_t *disable_extra_mem, int32_t *si_dma_duration, uint32_t *emumode, int32_t *no_compiled_jump)
static osal_inline void netplay_sync_settings(uint32_t *count_per_op, uint32_t *count_per_op_denom_pot, uint32_t *disable_extra_mem, int32_t *si_dma_duration, uint32_t *emumode, int32_t *no_compiled_jump)
{
}