mirror of
https://github.com/mupen64plus/mupen64plus-rsp-cxd4.git
synced 2024-05-13 09:49:42 -04:00
Add libretro NEON optimizations
credits: https://github.com/libretro/parallel-n64/tree/master/mupen64plus-rsp-cxd4
This commit is contained in:
Francisco Zurita
parent
c904e8f70e
commit
cc6b8833e3
11
my_types.h
11
my_types.h
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@ -32,6 +32,11 @@
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#ifndef _MY_TYPES_H_
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#define _MY_TYPES_H_
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#if defined(USE_SSE2NEON) && defined(__ARM_NEON__)
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#include "sse2neon/SSE2NEON.h"
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#define ARCH_MIN_SSE2
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#endif
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/*
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* This is the only method we really need to care about for defining types.
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*
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@ -493,4 +498,10 @@ typedef struct {
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} MIPS_type_J;
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#endif
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#if defined(__arm__) && (defined(__GNUC__) || defined(__clang__))
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#define COMPILER_FENCE() __asm__ __volatile__("":::"memory")
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#else
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#define COMPILER_FENCE()
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#endif
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#endif
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1067
sse2neon/SSE2NEON.h
Normal file
1067
sse2neon/SSE2NEON.h
Normal file
File diff suppressed because it is too large
Load diff
16
su.c
16
su.c
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@ -1825,7 +1825,7 @@ PROFILE_MODE void MWC2_load(u32 inst)
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const unsigned int vt = (inst >> 16) % (1 << 5);
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const unsigned int element = (inst >> 7) % (1 << 4);
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#ifdef ARCH_MIN_SSE2
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#if defined(ARCH_MIN_SSE2) && !defined(SSE2NEON)
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offset = (s16)inst;
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offset <<= 5 + 4; /* safe on x86, skips 5-bit rd, 4-bit element */
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offset >>= 5 + 4;
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@ -1841,7 +1841,7 @@ PROFILE_MODE void MWC2_store(u32 inst)
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const unsigned int vt = (inst >> 16) % (1 << 5);
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const unsigned int element = (inst >> 7) % (1 << 4);
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#ifdef ARCH_MIN_SSE2
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#if defined(ARCH_MIN_SSE2) && !defined(SSE2NEON)
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offset = (s16)inst;
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offset <<= 5 + 4; /* safe on x86, skips 5-bit rd, 4-bit element */
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offset >>= 5 + 4;
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@ -1911,6 +1911,12 @@ PROFILE_MODE void COP2(u32 inst)
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case 022:
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case 023:
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#ifdef ARCH_MIN_SSE2
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#ifdef __ARM_NEON__
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target = (v16)vld1q_u16(&VR[vt][0 + op - 0x12]);
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target = (v16)vshlq_n_u32((uint32x4_t)target, 16);
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target = (v16)vorrq_u16((uint16x8_t)target,
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(uint16x8_t)vshrq_n_u32((uint32x4_t)target, 16));
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#else
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shuffle_temporary[0] = VR[vt][0 + op - 0x12];
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shuffle_temporary[2] = VR[vt][2 + op - 0x12];
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shuffle_temporary[4] = VR[vt][4 + op - 0x12];
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@ -1918,6 +1924,7 @@ PROFILE_MODE void COP2(u32 inst)
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target = *(v16 *)(&shuffle_temporary[0]);
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target = _mm_shufflehi_epi16(target, _MM_SHUFFLE(2, 2, 0, 0));
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target = _mm_shufflelo_epi16(target, _MM_SHUFFLE(2, 2, 0, 0));
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#endif
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*(v16 *)(VR[vd]) = COP2_C2[func](*(v16 *)VR[vs], target);
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#else
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for (i = 0; i < N; i++)
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@ -1931,11 +1938,16 @@ PROFILE_MODE void COP2(u32 inst)
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case 026:
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case 027:
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#ifdef ARCH_MIN_SSE2
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#ifdef __ARM_NEON__
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target = (v16)vcombine_s16(vdup_n_s16(VR[vt][0 + op - 0x14]),
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vdup_n_s16(VR[vt][4 + op - 0x14]));
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#else
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target = _mm_setzero_si128();
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target = _mm_insert_epi16(target, VR[vt][0 + op - 0x14], 0);
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target = _mm_insert_epi16(target, VR[vt][4 + op - 0x14], 4);
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target = _mm_shufflehi_epi16(target, _MM_SHUFFLE(0, 0, 0, 0));
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target = _mm_shufflelo_epi16(target, _MM_SHUFFLE(0, 0, 0, 0));
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#endif
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*(v16 *)(VR[vd]) = COP2_C2[func](*(v16 *)VR[vs], target);
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#else
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for (i = 0; i < N; i++)
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2
su.h
2
su.h
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@ -182,7 +182,7 @@ extern void set_PC(unsigned int address);
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*
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* Some of these also will only work assuming 2's complement (e.g., Intel).
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*/
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#if defined(ARCH_MIN_SSE2)
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#if defined(ARCH_MIN_SSE2) && !defined(SSE2NEON)
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#define MASK_SA(sa) (sa)
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#define IW_RD(inst) ((u16)(inst) >> 11)
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#define SIGNED_IMM16(imm) (s16)(imm)
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5
vu/add.c
5
vu/add.c
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@ -227,6 +227,7 @@ VECTOR_OPERATION VADD(v16 vs, v16 vt)
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#endif
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clr_ci(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -251,6 +252,7 @@ VECTOR_OPERATION VSUB(v16 vs, v16 vt)
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#endif
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clr_bi(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -275,6 +277,7 @@ VECTOR_OPERATION VABS(v16 vs, v16 vt)
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#endif
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do_abs(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -299,6 +302,7 @@ VECTOR_OPERATION VADDC(v16 vs, v16 vt)
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#endif
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set_co(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -323,6 +327,7 @@ VECTOR_OPERATION VSUBC(v16 vs, v16 vt)
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#endif
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set_bo(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -1139,6 +1139,7 @@ VECTOR_OPERATION VRCP(v16 vs, v16 vt)
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VR[result][source & 07] = (i16)DivOut;
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DPH = SP_DIV_PRECISION_SINGLE;
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VR[result];
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return (vs);
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#else
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@ -1166,6 +1167,7 @@ VECTOR_OPERATION VRCPL(v16 vs, v16 vt)
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VR[result][source & 07] = (i16)DivOut;
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DPH = SP_DIV_PRECISION_SINGLE;
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VR[result];
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return (vs);
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#else
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@ -1191,6 +1193,7 @@ VECTOR_OPERATION VRCPH(v16 vs, v16 vt)
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VR[result][source & 07] = DivOut >> 16;
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DPH = SP_DIV_PRECISION_DOUBLE;
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VR[result];
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return (vs);
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#else
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@ -1213,6 +1216,7 @@ VECTOR_OPERATION VMOV(v16 vs, v16 vt)
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#endif
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VR[result][source & 07] = VACC_L[element];
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VR[result];
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return (vs);
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#else
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@ -1239,6 +1243,7 @@ VECTOR_OPERATION VRSQ(v16 vs, v16 vt)
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VR[result][source & 07] = (i16)DivOut;
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DPH = SP_DIV_PRECISION_SINGLE;
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VR[result];
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return (vs);
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#else
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@ -1266,6 +1271,7 @@ VECTOR_OPERATION VRSQL(v16 vs, v16 vt)
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VR[result][source & 07] = (i16)DivOut;
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DPH = SP_DIV_PRECISION_SINGLE;
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VR[result];
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return (vs);
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#else
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@ -1291,6 +1297,7 @@ VECTOR_OPERATION VRSQH(v16 vs, v16 vt)
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VR[result][source & 07] = DivOut >> 16;
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DPH = SP_DIV_PRECISION_DOUBLE;
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VR[result];
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return (vs);
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#else
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@ -447,6 +447,7 @@ VECTOR_OPERATION VMACF(v16 vs, v16 vt)
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#endif
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do_macf(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -471,6 +472,7 @@ VECTOR_OPERATION VMACU(v16 vs, v16 vt)
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#endif
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do_macu(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -360,6 +360,7 @@ VECTOR_OPERATION VLT(v16 vs, v16 vt)
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#endif
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do_lt(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -384,6 +385,7 @@ VECTOR_OPERATION VEQ(v16 vs, v16 vt)
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#endif
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do_eq(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -408,6 +410,7 @@ VECTOR_OPERATION VNE(v16 vs, v16 vt)
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#endif
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do_ne(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -432,6 +435,7 @@ VECTOR_OPERATION VGE(v16 vs, v16 vt)
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#endif
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do_ge(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -456,6 +460,7 @@ VECTOR_OPERATION VCL(v16 vs, v16 vt)
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#endif
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do_cl(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -480,6 +485,7 @@ VECTOR_OPERATION VCH(v16 vs, v16 vt)
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#endif
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do_ch(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -504,6 +510,7 @@ VECTOR_OPERATION VCR(v16 vs, v16 vt)
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#endif
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do_cr(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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@ -528,6 +535,7 @@ VECTOR_OPERATION VMRG(v16 vs, v16 vt)
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#endif
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do_mrg(VD, VS, VT);
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#ifdef ARCH_MIN_SSE2
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COMPILER_FENCE();
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vs = *(v16 *)VD;
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return (vs);
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#else
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