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Merge branch 'master' into dynarec_v2

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This commit is contained in:
Dillon Beliveau 2023-07-16 18:52:51 -07:00
parent 7d556f46a9 744d8ed655
commit 09263a71c7
15 changed files with 81 additions and 80 deletions
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2
CMakeLists.txt
View file

@ -5,7 +5,7 @@ if (${CMAKE_HOST_SYSTEM_NAME} MATCHES "Darwin")
set(MACOSX TRUE)
endif()
set(DEFAULT_C_COMP_OPTIONS -mssse3 -msse4.1 -Werror=switch)
set(DEFAULT_C_COMP_OPTIONS -mssse3 -msse4.1 -Werror=switch -Werror=format)
set(DEFAULT_C_LINK_OPTIONS "")
# Asan

1
src/common/util.h
View file

@ -1,6 +1,7 @@
#ifndef __UTIL_H__
#define __UTIL_H__
#include <stdint.h>
#include <inttypes.h>
#include <stdbool.h>
#include <stdio.h>

6
src/cpu/dynarec/dynarec.c
View file

@ -95,7 +95,7 @@ int n64_dynarec_step() {
#ifdef LOG_ENABLED
static long total_blocks_run;
logdebug("Running block at 0x%016lX - block run #%ld - block FP: 0x%016lX", N64CPU.pc, ++total_blocks_run, (uintptr_t)block->run);
logdebug("Running block at 0x%016" PRIX64 " - block run #%ld - block FP: 0x%016" PRIX64, N64CPU.pc, ++total_blocks_run, (uintptr_t)block->run);
#endif
N64CPU.exception = false;
int taken;
@ -113,14 +113,14 @@ int n64_dynarec_step() {
#ifdef N64_LOG_JIT_SYNC_POINTS
printf("JITSYNC %d %08X ", taken, N64CPU.pc);
for (int i = 0; i < 32; i++) {
printf("%016lX", N64CPU.gpr[i]);
printf("%016" PRIX64, N64CPU.gpr[i]);
if (i != 31) {
printf(" ");
}
}
printf("\n");
#endif
logdebug("Done running block - took %d cycles - pc is now 0x%016lX", taken, N64CPU.pc);
logdebug("Done running block - took %d cycles - pc is now 0x%016" PRIX64, taken, N64CPU.pc);
return taken * CYCLES_PER_INSTR;
}

22
src/cpu/mips_instructions.c
View file

@ -78,7 +78,7 @@ MIPS_INSTR(mips_bne) {
MIPS_INSTR(mips_bnel) {
u64 rs = get_register(instruction.i.rs);
u64 rt = get_register(instruction.i.rt);
logtrace("Branch if: 0x%08lX != 0x%08lX", rs, rt);
logtrace("Branch if: 0x%08" PRIX64 " != 0x%08" PRIX64, rs, rt);
conditional_branch_likely(instruction.i.immediate, rs != rt);
}
@ -107,7 +107,7 @@ MIPS_INSTR(mips_jal) {
MIPS_INSTR(mips_slti) {
s16 immediate = instruction.i.immediate;
logtrace("Set if %ld < %d", get_register(instruction.i.rs), immediate);
logtrace("Set if %" PRId64 " < %d", get_register(instruction.i.rs), immediate);
s64 reg = get_register(instruction.i.rs);
if (reg < immediate) {
set_register(instruction.i.rt, 1);
@ -118,7 +118,7 @@ MIPS_INSTR(mips_slti) {
MIPS_INSTR(mips_sltiu) {
s16 immediate = instruction.i.immediate;
logtrace("Set if %ld < %d", get_register(instruction.i.rs), immediate);
logtrace("Set if %" PRId64 " < %d", get_register(instruction.i.rs), immediate);
if (get_register(instruction.i.rs) < immediate) {
set_register(instruction.i.rt, 1);
} else {
@ -193,7 +193,7 @@ MIPS_INSTR(mips_lhu) {
logtrace("LHU offset: %d", offset);
u64 address = get_register(instruction.i.rs) + offset;
if ((address & 0b1) > 0) {
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016lX", address);
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016" PRIX64, address);
}
u32 physical;
@ -210,7 +210,7 @@ MIPS_INSTR(mips_lh) {
s16 offset = instruction.i.immediate;
u64 address = get_register(instruction.i.rs) + offset;
if ((address & 0b1) > 0) {
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016lX", address);
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016" PRIX64, address);
}
u32 physical;
@ -246,7 +246,7 @@ MIPS_INSTR(mips_lwu) {
s16 offset = instruction.i.immediate;
u64 address = get_register(instruction.i.rs) + offset;
if ((address & 0b11) > 0) {
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016lX", address);
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016" PRIX64, address);
}
u32 physical;
@ -511,7 +511,7 @@ MIPS_INSTR(mips_ll) {
if ((address & 0b11) > 0) {
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016lX", address);
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016" PRIX64, address);
}
set_register(instruction.i.rt, (s64)result);
@ -539,7 +539,7 @@ MIPS_INSTR(mips_lld) {
} else {
u64 result = n64_read_physical_dword(physical);
if ((address & 0b111) > 0) {
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016lX", address);
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016" PRIX64, address);
}
set_register(instruction.i.rt, result);
@ -556,7 +556,7 @@ MIPS_INSTR(mips_sc) {
// Exception takes precedence over the instruction failing
if ((address & 0b11) > 0) {
logfatal("TODO: throw an 'address error' exception! Tried to store to unaligned address 0x%016lX", address);
logfatal("TODO: throw an 'address error' exception! Tried to store to unaligned address 0x%016" PRIX64, address);
}
if (N64CPU.llbit) {
@ -588,7 +588,7 @@ MIPS_INSTR(mips_scd) {
// Exception takes precedence over the instruction failing
if ((address & 0b111) > 0) {
logfatal("TODO: throw an 'address error' exception! Tried to store to unaligned address 0x%016lX", address);
logfatal("TODO: throw an 'address error' exception! Tried to store to unaligned address 0x%016" PRIX64, address);
}
if (N64CPU.llbit) {
@ -878,7 +878,7 @@ MIPS_INSTR(mips_spc_sltu) {
u64 op1 = get_register(instruction.r.rs);
u64 op2 = get_register(instruction.r.rt);
logtrace("Set if %lu < %lu", op1, op2);
logtrace("Set if %" PRIu64 " < %" PRIu64, op1, op2);
if (op1 < op2) {
set_register(instruction.r.rd, 1);
} else {

4
src/cpu/r4300i.c
View file

@ -133,7 +133,7 @@ void r4300i_handle_exception(u64 pc, u32 code, int coprocessor_error) {
}
cp0_status_updated();
N64CPU.exception = true; // For dynarec
loginfo("Exception handled, PC is now %016lX", N64CPU.pc);
loginfo("Exception handled, PC is now %016" PRIX64, N64CPU.pc);
}
INLINE mipsinstr_handler_t r4300i_cp0_decode(u64 pc, mips_instruction_t instr) {
@ -670,7 +670,7 @@ mipsinstr_handler_t r4300i_instruction_decode(u64 pc, mips_instruction_t instr)
char buf[50];
if (n64_log_verbosity >= LOG_VERBOSITY_DEBUG) {
disassemble(pc, instr.raw, buf, 50);
logdebug("[0x%016lX]=0x%08X %s", pc, instr.raw, buf);
logdebug("[0x%016" PRIX64 "]=0x%08X %s", pc, instr.raw, buf);
}
#endif
if (unlikely(instr.raw == 0)) {

6
src/cpu/r4300i_register_access.h
View file

@ -5,14 +5,14 @@
#include <system/scheduler_utils.h>
INLINE void set_register(u8 r, u64 value) {
logtrace("Setting $%s (r%d) to [0x%016lX]", register_names[r], r, value);
logtrace("Setting $%s (r%d) to [0x%016" PRIX64 "]", register_names[r], r, value);
N64CPU.gpr[r] = value;
N64CPU.gpr[0] = 0;
}
INLINE u64 get_register(u8 r) {
u64 value = N64CPU.gpr[r];
logtrace("Reading $%s (r%d): 0x%016lX", register_names[r], r, value);
logtrace("Reading $%s (r%d): 0x%016" PRIX64, register_names[r], r, value);
return value;
}
@ -62,7 +62,7 @@ INLINE void set_cp0_register_word(u8 r, u32 value) {
N64CPU.cp0.tag_hi = value;
break;
case R4300I_CP0_REG_COMPARE:
loginfo("$Compare written with 0x%08X (count is now 0x%08lX)", value, N64CPU.cp0.count);
loginfo("$Compare written with 0x%08X (count is now 0x%08" PRIX64 ")", value, N64CPU.cp0.count);
N64CPU.cp0.cause.ip7 = false;
N64CPU.cp0.compare = value;
reschedule_compare_interrupt(0);

14
src/debugger/debugger.c
View file

@ -181,20 +181,20 @@ ssize_t n64_debug_get_memory(void* user_data, char* buffer, size_t length, u32 a
ssize_t n64_debug_get_register_value(void* user_data, char * buffer, size_t buffer_length, int reg) {
switch (reg) {
case 0 ... 31:
return snprintf(buffer, buffer_length, "%016lx", N64CPU.gpr[reg]);
return snprintf(buffer, buffer_length, "%016" PRIX64, N64CPU.gpr[reg]);
case 32:
return snprintf(buffer, buffer_length, "%08x", N64CP0.status.raw);
case 33:
return snprintf(buffer, buffer_length, "%016lx", N64CPU.mult_lo);
return snprintf(buffer, buffer_length, "%016" PRIX64, N64CPU.mult_lo);
case 34:
return snprintf(buffer, buffer_length, "%016lx", N64CPU.mult_hi);
return snprintf(buffer, buffer_length, "%016" PRIX64, N64CPU.mult_hi);
case 35:
return snprintf(buffer, buffer_length, "%016lx", N64CP0.bad_vaddr);
return snprintf(buffer, buffer_length, "%016" PRIX64, N64CP0.bad_vaddr);
case 36:
return snprintf(buffer, buffer_length, "%08x", N64CP0.cause.raw);
case 37:
printf("Sending PC: 0x%016lX\n", N64CPU.pc);
return snprintf(buffer, buffer_length, "%016lx", N64CPU.pc);
printf("Sending PC: 0x%016" PRIX64 "\n", N64CPU.pc);
return snprintf(buffer, buffer_length, "%016" PRIX64, N64CPU.pc);
case 38 ... 71: // TODO FPU stuff
return snprintf(buffer, buffer_length, "%08x", 0);
default:
@ -211,7 +211,7 @@ ssize_t n64_debug_get_general_registers(void* user_data, char * buffer, size_t b
logfatal("Too big!");
}
u64 reg = N64CPU.gpr[i];
printed += snprintf(buffer + ofs, buffer_length - ofs, "%016lx", reg);
printed += snprintf(buffer + ofs, buffer_length - ofs, "%016" PRIX64, reg);
}
return printed;
}

4
src/imgui/imgui_ui.cpp
View file

@ -186,7 +186,7 @@ void render_metrics_window() {
ImPlot::EndPlot();
}
ImGui::Text("Block compilations this frame: %ld", get_metric(METRIC_BLOCK_COMPILATION));
ImGui::Text("Block compilations this frame: %" PRId64, get_metric(METRIC_BLOCK_COMPILATION));
ImPlot::SetNextAxisLimits(ImAxis_Y1, 0, block_compilations.max(), ImGuiCond_Always);
ImPlot::SetNextAxisLimits(ImAxis_X1, 0, METRICS_HISTORY_ITEMS, ImGuiCond_Always);
if (ImPlot::BeginPlot("Block Compilations Per Frame")) {
@ -209,7 +209,7 @@ void render_metrics_window() {
ImPlot::EndPlot();
}
ImGui::Text("Audio stream bytes available: %ld", get_metric(METRIC_AUDIOSTREAM_AVAILABLE));
ImGui::Text("Audio stream bytes available: %" PRId64, get_metric(METRIC_AUDIOSTREAM_AVAILABLE));
ImPlot::SetNextAxisLimits(ImAxis_Y1, 0, audiostream_bytes_available.max(), ImGuiCond_Always);
ImPlot::SetNextAxisLimits(ImAxis_X1, 0, METRICS_HISTORY_ITEMS, ImGuiCond_Always);
if (ImPlot::BeginPlot("Audio Stream Bytes Available")) {

16
src/interface/pi.c
View file

@ -71,7 +71,7 @@ u8 pi_get_domain(u32 address) {
case REGION_CART_1_2: {
u32 index = BYTE_ADDRESS(address) - SREGION_CART_1_2;
if (index >= n64sys.mem.rom.size) {
logwarn("Address 0x%08X accessed an index %d/0x%X outside the bounds of the ROM! (%ld/0x%lX)", address, index, index, n64sys.mem.rom.size, n64sys.mem.rom.size);
logwarn("Address 0x%08X accessed an index %d/0x%X outside the bounds of the ROM! (%zu/0x%zX)", address, index, index, n64sys.mem.rom.size, n64sys.mem.rom.size);
return 0xFF;
}
return n64sys.mem.rom.rom[index];
@ -129,7 +129,7 @@ void write_word_pireg(u32 address, u32 value) {
}
logdebug("DMA requested at PC 0x%016lX from 0x%08X to 0x%08X (DRAM to CART), with a length of %d", N64CPU.pc, dram_addr, cart_addr, length);
logdebug("DMA requested at PC 0x%016" PRIX64 " from 0x%08X to 0x%08X (DRAM to CART), with a length of %d", N64CPU.pc, dram_addr, cart_addr, length);
// TODO: takes 9 cycles per byte to run in reality
for (int i = 0; i < length; i++) {
@ -165,7 +165,7 @@ void write_word_pireg(u32 address, u32 value) {
logfatal("Cart address too low! 0x%08X masked to 0x%08X\n", n64sys.mem.pi_reg[PI_CART_ADDR_REG], cart_addr);
}
logdebug("DMA requested at PC 0x%016lX from 0x%08X to 0x%08X (CART to DRAM), with a length of %d", N64CPU.pc, cart_addr, dram_addr, length);
logdebug("DMA requested at PC 0x%016" PRIX64 " from 0x%08X to 0x%08X (CART to DRAM), with a length of %d", N64CPU.pc, cart_addr, dram_addr, length);
if (is_flash(n64sys.mem.save_type) && cart_addr >= 0x08000000 && cart_addr < 0x08010000) {
// Special case for Flash DMAs
@ -300,7 +300,7 @@ u8 read_byte_pibus(u32 address) {
address = (address + 2) & ~2;
u32 index = BYTE_ADDRESS(address) - SREGION_CART_1_2;
if (index > n64sys.mem.rom.size) {
logwarn("Address 0x%08X accessed an index %d/0x%X outside the bounds of the ROM! (%ld/0x%lX)", address, index, index, n64sys.mem.rom.size, n64sys.mem.rom.size);
logwarn("Address 0x%08X accessed an index %d/0x%X outside the bounds of the ROM! (%zd/0x%zX)", address, index, index, n64sys.mem.rom.size, n64sys.mem.rom.size);
return 0xFF;
}
return n64sys.mem.rom.rom[index];
@ -448,13 +448,13 @@ void write_dword_pibus(u32 address, u64 value) {
}
switch (address) {
case REGION_CART_2_1:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_CART_2_1", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_CART_2_1", value, address);
case REGION_CART_1_1:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_CART_1_1", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_CART_1_1", value, address);
case REGION_CART_2_2:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_CART_2_2", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_CART_2_2", value, address);
case REGION_CART_1_2:
logwarn("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_CART_1_2", value, address);
logwarn("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_CART_1_2", value, address);
break;
default:
logfatal("write_dword_pibus(): Access to non-PI address %08X", address);

36
src/mem/n64bus.c
View file

@ -28,7 +28,7 @@ u64 get_vpn(u64 address, u32 page_mask_raw) {
/* Keeping this in case I need it again
void dump_tlb(u64 vaddr) {
printf("TLB error at address %016lX and PC %016lX, dumping TLB state:\n\n", vaddr, N64CPU.pc);
printf("TLB error at address %016" PRIX64 " and PC %016" PRIX64 ", dumping TLB state:\n\n", vaddr, N64CPU.pc);
printf(" entry VPN vaddr VPN page size lo0 valid lo1 valid\n");
for (int i = 0; i < 32; i++) {
tlb_entry_t entry = N64CP0.tlb[i];
@ -286,14 +286,14 @@ void n64_write_physical_dword(u32 address, u64 value) {
if (address & 0b111) {
logfatal("Tried to write to unaligned DWORD");
}
logdebug("Writing 0x%016lX to [0x%08X]", value, address);
logdebug("Writing 0x%016" PRIX64 " to [0x%08X]", value, address);
invalidate_dynarec_page(address);
switch (address) {
case REGION_RDRAM:
dword_to_byte_array((u8*) &n64sys.mem.rdram, DWORD_ADDRESS(address) - SREGION_RDRAM, value);
break;
case REGION_RDRAM_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_RDRAM_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_RDRAM_REGS", value, address);
break;
case REGION_RDRAM_UNUSED:
return;
@ -308,51 +308,51 @@ void n64_write_physical_dword(u32 address, u64 value) {
break;
}
case REGION_SP_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_SP_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_SP_REGS", value, address);
break;
case REGION_DP_COMMAND_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_DP_COMMAND_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_DP_COMMAND_REGS", value, address);
case REGION_DP_SPAN_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_DP_SPAN_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_DP_SPAN_REGS", value, address);
case REGION_MI_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_MI_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_MI_REGS", value, address);
break;
case REGION_VI_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_VI_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_VI_REGS", value, address);
break;
case REGION_AI_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_AI_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_AI_REGS", value, address);
break;
case REGION_PI_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_PI_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_PI_REGS", value, address);
break;
case REGION_RI_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_RI_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_RI_REGS", value, address);
break;
case REGION_SI_REGS:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_SI_REGS", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_SI_REGS", value, address);
break;
case REGION_UNUSED:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_UNUSED", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_UNUSED", value, address);
case REGION_CART:
write_dword_pibus(address, value);
break;
case REGION_PIF_BOOT:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_PIF_BOOT", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_PIF_BOOT", value, address);
case REGION_PIF_RAM:
dword_to_byte_array(n64sys.mem.pif_ram, address - SREGION_PIF_RAM, htobe64(value));
process_pif_command();
logfatal("Writing dword 0x%016lX to address 0x%08X in region: REGION_PIF_RAM", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in region: REGION_PIF_RAM", value, address);
break;
case REGION_RESERVED:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_RESERVED", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_RESERVED", value, address);
case REGION_CART_1_3:
logfatal("Writing dword 0x%016lX to address 0x%08X in unsupported region: REGION_CART_1_3", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to address 0x%08X in unsupported region: REGION_CART_1_3", value, address);
case REGION_SYSAD_DEVICE:
logfatal("This is a virtual address!");
break;
default:
logfatal("Writing dword 0x%016lX to unknown address: 0x%08X", value, address);
logfatal("Writing dword 0x%016" PRIX64 " to unknown address: 0x%08X", value, address);
}
}

14
src/mem/n64bus.h
View file

@ -93,11 +93,11 @@ INLINE bool resolve_virtual_address_64bit(u64 address, bus_access_t bus_access,
return tlb_probe(address, bus_access, physical, NULL);
case REGION_XKPHYS: {
if (!N64CP0.kernel_mode) {
logfatal("Access to XKPHYS address 0x%016lX when outside kernel mode!", address);
logfatal("Access to XKPHYS address 0x%016" PRIX64 " when outside kernel mode!", address);
}
u8 high_two_bits = (address >> 62) & 0b11;
if (high_two_bits != 0b10) {
logfatal("Access to XKPHYS address 0x%016lX with high two bits != 0b10!", address);
logfatal("Access to XKPHYS address 0x%016" PRIX64 " with high two bits != 0b10!", address);
}
u8 subsegment = (address >> 59) & 0b11;
bool cached = subsegment != 2;
@ -119,16 +119,16 @@ INLINE bool resolve_virtual_address_64bit(u64 address, bus_access_t bus_access,
// Identical to kseg0 in 32 bit mode.
// Unmapped translation. Subtract the base address of the space to get the physical address.
*physical = address - SVREGION_KSEG0; // Implies cutting off the high 32 bits
logtrace("CKSEG0: Translated 0x%016lX to 0x%08X", address, *physical);
logtrace("CKSEG0: Translated 0x%016" PRIX64 " to 0x%08X", address, *physical);
break;
case REGION_CKSEG1:
// Identical to kseg1 in 32 bit mode.
// Unmapped translation. Subtract the base address of the space to get the physical address.
*physical = address - SVREGION_KSEG1; // Implies cutting off the high 32 bits
logtrace("KSEG1: Translated 0x%016lX to 0x%08X", address, *physical);
logtrace("KSEG1: Translated 0x%016" PRIX64 " to 0x%08X", address, *physical);
break;
case REGION_CKSSEG:
logfatal("Resolving virtual address 0x%016lX (REGION_CKSSEG) in 64 bit mode", address);
logfatal("Resolving virtual address 0x%016" PRIX64 " (REGION_CKSSEG) in 64 bit mode", address);
case REGION_CKSEG3:
return tlb_probe(address, bus_access, physical, NULL);
case REGION_XBAD1:
@ -137,7 +137,7 @@ INLINE bool resolve_virtual_address_64bit(u64 address, bus_access_t bus_access,
N64CP0.tlb_error = TLB_ERROR_DISALLOWED_ADDRESS;
return false;
default:
logfatal("Resolving virtual address 0x%016lX in 64 bit mode", address);
logfatal("Resolving virtual address 0x%016" PRIX64 " in 64 bit mode", address);
}
return true;
@ -180,7 +180,7 @@ INLINE bool resolve_virtual_address(u64 virtual, bus_access_t bus_access, u32* p
INLINE u32 resolve_virtual_address_or_die(u64 virtual, bus_access_t bus_access) {
u32 physical;
if (!resolve_virtual_address(virtual, bus_access, &physical)) {
logfatal("Unhandled TLB exception at 0x%016lX! Stop calling resolve_virtual_address_or_die() here!", virtual);
logfatal("Unhandled TLB exception at 0x%016" PRIX64 "! Stop calling resolve_virtual_address_or_die() here!", virtual);
}
return physical;
}

6
src/rdp/softrdp.cpp
View file

@ -1055,7 +1055,7 @@ DEF_RDP_COMMAND(fill_rectangle) {
DEF_RDP_COMMAND(set_fill_color) {
rdp->fill_color = get_bits(buffer[0], 31, 0);
logalways("Fill color cmd word: %016lX", buffer[0]);
logalways("Fill color cmd word: %016" PRIX64, buffer[0]);
logalways("Fill color: 0x%08X", rdp->fill_color);
}
@ -1081,7 +1081,7 @@ DEF_RDP_COMMAND(set_env_color) {
}
DEF_RDP_COMMAND(set_combine) {
logalways("Set combine: %016lX", buffer[0]);
logalways("Set combine: %016" PRIX64, buffer[0]);
rdp->combine.sub_a_R_0 = get_bits(buffer[0], 55, 52);
rdp->combine.mul_R_0 = get_bits(buffer[0], 51, 47);
rdp->combine.sub_a_A_0 = get_bits(buffer[0], 46, 44);
@ -1120,7 +1120,7 @@ DEF_RDP_COMMAND(set_mask_image) {
}
DEF_RDP_COMMAND(set_color_image) {
logalways("Set color image %016lX:", buffer[0]);
logalways("Set color image %016" PRIX64 ":", buffer[0]);
rdp->color_image.format = get_bits(buffer[0], 55, 53);
rdp->color_image.size = get_bits(buffer[0], 52, 51);
rdp->color_image.width = get_bits(buffer[0], 41, 32) + 1;

12
src/tools/testcase_gen.c
View file

@ -62,12 +62,12 @@ void gen_imm_rsrti(char* name, mipsinstr_handler_t handler) {
printf("align(8)\n");
printf("RegArgs:\n");
for (int i = 0; i < num_cases; i++) {
printf("\tdd $%016lX\n", regargs[i]);
printf("\tdd $%016" PRIX64 "\n", regargs[i]);
}
printf("align(8)\n");
printf("Expected:\n");
for (int i = 0; i < num_cases; i++) {
printf("\tdd $%016lX\n", expected_result[i]);
printf("\tdd $%016" PRIX64 "\n", expected_result[i]);
}
printf("align(2)\n");
printf("\nImmArgs:\n");
@ -120,12 +120,12 @@ void gen_shift(char* name, mipsinstr_handler_t handler) {
printf("align(8)\n");
printf("RegArgs:\n");
for (int i = 0; i < num_cases; i++) {
printf("\tdd $%016lX\n", regargs[i]);
printf("\tdd $%016" PRIX64 "\n", regargs[i]);
}
printf("align(8)\n");
printf("Expected:\n");
for (int i = 0; i < num_results; i++) {
printf("\tdd $%016lX\n", expected_result[i]);
printf("\tdd $%016" PRIX64 "\n", expected_result[i]);
}
}
@ -177,12 +177,12 @@ void gen_rs_rt_rd(char* name, mipsinstr_handler_t handler) {
printf("align(8)\n");
printf("RegArgs:\n");
for (int i = 0; i < num_cases; i++) {
printf("\tdd $%016lX\n", regargs[i]);
printf("\tdd $%016" PRIX64 "\n", regargs[i]);
}
printf("align(8)\n");
printf("Expected:\n");
for (int i = 0; i < (num_cases * num_cases); i++) {
printf("\tdd $%016lX\n", expected_result[i]);
printf("\tdd $%016" PRIX64 "\n", expected_result[i]);
}
}

2
tests/test_rom.c
View file

@ -44,7 +44,7 @@ int main(int argc, char** argv) {
set_pc_word_r4300i(n64sys.mem.rom.header.program_counter);
loginfo("Initial PC: 0x%016lX\n", N64CPU.pc);
loginfo("Initial PC: 0x%016" PRIX64 "\n", N64CPU.pc);
int steps = 0;
bool use_dynarec = recomp(argv[2]);

16
tests/unit.h
View file

@ -115,9 +115,9 @@ void test_instr_branch(case_branch_instr test_case, mipsinstr_handler_t instr, c
bool taken = N64CPU.next_pc == 4;
if (taken != test_case.taken) {
failed("%s: (r%d)0x%016lX, (r%d)0x%016lX | Expected: %s but got %s", instr_name, r1, test_case.r1, r2, test_case.r2, taken_macro(test_case.taken), taken_macro(taken))
failed("%s: (r%d)0x%016" PRIX64 ", (r%d)0x%016" PRIX64 " | Expected: %s but got %s", instr_name, r1, test_case.r1, r2, test_case.r2, taken_macro(test_case.taken), taken_macro(taken))
} else if (SHOULD_LOG_PASSED_TESTS) {
passed("%s: (r%d)0x%016lX, (r%d)0x%016lX | Expected: %s and got %s", instr_name, r1, test_case.r1, r2, test_case.r2, taken_macro(test_case.taken), taken_macro(taken))
passed("%s: (r%d)0x%016" PRIX64 ", (r%d)0x%016" PRIX64 " | Expected: %s and got %s", instr_name, r1, test_case.r1, r2, test_case.r2, taken_macro(test_case.taken), taken_macro(taken))
}
}
@ -139,9 +139,9 @@ void test_instr_sa(case_sa_instr test_case, mipsinstr_handler_t instr, const cha
u64 expected = test_case.output;
if (expected != actual) {
failed("%s: (r%d)0x%016lX, 0x%02X | Expected: 0x%016lX but got 0x%016lX", instr_name, rinput, test_case.input, test_case.sa, expected, actual)
failed("%s: (r%d)0x%016" PRIX64 ", 0x%02X | Expected: 0x%016" PRIX64 " but got 0x%016" PRIX64, instr_name, rinput, test_case.input, test_case.sa, expected, actual)
} else if (SHOULD_LOG_PASSED_TESTS) {
passed("%s: (r%d)0x%016lX, 0x%02X | Expected: 0x%016lX and got 0x%016lX", instr_name, rinput, test_case.input, test_case.sa, expected, actual)
passed("%s: (r%d)0x%016" PRIX64 ", 0x%02X | Expected: 0x%016" PRIX64 " and got 0x%016" PRIX64, instr_name, rinput, test_case.input, test_case.sa, expected, actual)
}
}
@ -166,12 +166,12 @@ void test_instr_lohi(case_lohi_instr test_case, mipsinstr_handler_t instr, const
u64 actual_hi = N64CPU.mult_hi;
if (expected_lo != actual_lo) {
failed("%s: (r%d)0x%016lX, (r%d)0x%016lX | LO Expected: 0x%016lX but got 0x%016lX", instr_name, r1, test_case.r1, r2, test_case.r2, expected_lo, actual_lo)
failed("%s: (r%d)0x%016" PRIX64 ", (r%d)0x%016" PRIX64 " | LO Expected: 0x%016" PRIX64 " but got 0x%016" PRIX64, instr_name, r1, test_case.r1, r2, test_case.r2, expected_lo, actual_lo)
} else if (expected_hi != actual_hi) {
failed("%s: (r%d)0x%016lX, (r%d)0x%016lX | HI Expected: 0x%016lX but got 0x%016lX", instr_name, r1, test_case.r1, r2, test_case.r2, expected_hi, actual_hi)
failed("%s: (r%d)0x%016" PRIX64 ", (r%d)0x%016" PRIX64 " | HI Expected: 0x%016" PRIX64 " but got 0x%016" PRIX64, instr_name, r1, test_case.r1, r2, test_case.r2, expected_hi, actual_hi)
} else if (SHOULD_LOG_PASSED_TESTS) {
passed("%s: (r%d)0x%016lX, (r%d)0x%016lX | LO Expected: 0x%016lX and got 0x%016lX", instr_name, r1, test_case.r1, r2, test_case.r2, expected_lo, actual_lo)
passed("%s: (r%d)0x%016lX, (r%d)0x%016lX | HI Expected: 0x%016lX and got 0x%016lX", instr_name, r1, test_case.r1, r2, test_case.r2, expected_hi, actual_hi)
passed("%s: (r%d)0x%016" PRIX64 ", (r%d)0x%016" PRIX64 " | LO Expected: 0x%016" PRIX64 " and got 0x%016" PRIX64, instr_name, r1, test_case.r1, r2, test_case.r2, expected_lo, actual_lo)
passed("%s: (r%d)0x%016" PRIX64 ", (r%d)0x%016" PRIX64 " | HI Expected: 0x%016" PRIX64 " and got 0x%016" PRIX64, instr_name, r1, test_case.r1, r2, test_case.r2, expected_hi, actual_hi)
}
}