mirror of
https://github.com/Dillonb/n64.git
synced 2024-05-17 03:20:34 -04:00
implement data cache
This commit is contained in:
Dillon Beliveau
parent
4a727909bd
commit
1e461dc014
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@ -10,6 +10,7 @@ configure_file(../contrib/tools/dynasm/dasm_x86.lua dynasm/dasm_x86.lua COPYONLY
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add_library(r4300i
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r4300i.c r4300i.h r4300i_register_access.h
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cache.c cache.h
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mips_instructions.c mips_instructions.h
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fpu_instructions.c fpu_instructions.h
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tlb_instructions.c tlb_instructions.h
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92
src/cpu/cache.c
Normal file
92
src/cpu/cache.c
Normal file
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@ -0,0 +1,92 @@
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#include "cache.h"
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#include <system/n64system.h>
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#include <mem/mem_util.h>
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void writeback_dcache(u64 vaddr, u32 paddr) {
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int cache_line = get_dcache_line_index(vaddr);
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dcache_line_t* line = &N64CPU.dcache[cache_line];
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if (!line->valid) {
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logfatal("Writing back invalid dcache line");
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}
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u32 original_paddr = (line->ptag << 12) | (paddr & 0xFFF);
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u32 line_start = get_dcache_line_start(original_paddr);
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for (int i = 0; i < 16; i++) {
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n64sys.mem.rdram[line_start + i] = line->data[i];
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}
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line->dirty = false;
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}
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INLINE dcache_line_t* prep_dcache_line(u64 vaddr, u32 paddr) {
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int cache_line_index = get_dcache_line_index(vaddr);
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dcache_line_t* line = &N64CPU.dcache[cache_line_index];
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u32 ptag = get_paddr_ptag(paddr);
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bool valid = line->valid;
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bool ptag_matches = line->ptag == ptag;
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bool hit = valid && ptag_matches;
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bool dirty = line->dirty;
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// If the cache line is valid but dirty it contains data that is not written back to RAM yet.
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// If it's also not a hit, we are going to need to reload it next, so write it back.
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if (valid && dirty && !hit) {
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writeback_dcache(vaddr, paddr);
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}
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// If the cache line is not valid or it's not a hit, load it from RAM
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if (!valid || !hit) {
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u32 line_start = get_dcache_line_start(paddr);
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if (paddr < N64_RDRAM_SIZE) {
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for (int i = 0; i < 16; i++) {
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line->data[i] = n64sys.mem.rdram[line_start + i];
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}
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} else {
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logfatal("Implement me: Loading dcache from something other than RDRAM");
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}
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line->valid = true;
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line->dirty = false;
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line->ptag = ptag;
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line->index = cache_line_index;
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}
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return line;
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}
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u8 cache_read_byte(u64 vaddr, u32 paddr) {
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return prep_dcache_line(vaddr, paddr)->data[BYTE_ADDRESS(paddr & 0xF)];
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}
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void cache_write_byte(u64 vaddr, u32 paddr, u8 value) {
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dcache_line_t* line = prep_dcache_line(vaddr, paddr);
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line->data[BYTE_ADDRESS(paddr & 0xF)] = value;
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line->dirty = true;
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}
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u16 cache_read_half(u64 vaddr, u32 paddr) {
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return half_from_byte_array(prep_dcache_line(vaddr, paddr)->data, HALF_ADDRESS(paddr & 0xF));
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}
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void cache_write_half(u64 vaddr, u32 paddr, u16 value) {
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dcache_line_t* line = prep_dcache_line(vaddr, paddr);
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half_to_byte_array(line->data, HALF_ADDRESS(paddr & 0xF), value);
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line->dirty = true;
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}
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u32 cache_read_word(u64 vaddr, u32 paddr) {
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return word_from_byte_array(prep_dcache_line(vaddr, paddr)->data, WORD_ADDRESS(paddr & 0xF));
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}
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void cache_write_word(u64 vaddr, u32 paddr, u32 value) {
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dcache_line_t* line = prep_dcache_line(vaddr, paddr);
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word_to_byte_array(line->data, WORD_ADDRESS(paddr & 0xF), value);
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line->dirty = true;
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}
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u64 cache_read_dword(u64 vaddr, u32 paddr) {
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return dword_from_byte_array(prep_dcache_line(vaddr, paddr)->data, DWORD_ADDRESS(paddr & 0xF));
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}
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void cache_write_dword(u64 vaddr, u32 paddr, u64 value) {
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dcache_line_t* line = prep_dcache_line(vaddr, paddr);
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dword_to_byte_array(line->data, DWORD_ADDRESS(paddr & 0xF), value);
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line->dirty = true;
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}
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54
src/cpu/cache.h
Normal file
54
src/cpu/cache.h
Normal file
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@ -0,0 +1,54 @@
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#ifndef N64_CACHE_H
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#define N64_CACHE_H
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// #include <mem/n64bus.h>
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#include <util.h>
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typedef struct icache_line {
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bool valid;
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u32 ptag;
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// since the icache will only ever be accessed as u32, just store it as u32
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u32 data[8]; // 32 bytes, 8 words
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} icache_line_t;
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typedef struct dcache_line {
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bool valid;
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bool dirty;
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u32 ptag;
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u8 data[16];
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int index;
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} dcache_line_t;
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INLINE int get_icache_line_index(u64 vaddr) {
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return (vaddr >> 5) & 0x1FF;
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}
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INLINE u32 get_icache_line_start(u32 paddr) {
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return paddr & ~0x1F;
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}
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INLINE int get_dcache_line_index(u64 vaddr) {
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return (vaddr >> 4) & 0x1FF;
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}
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INLINE u32 get_dcache_line_start(u32 paddr) {
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return paddr & ~0xF;
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}
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INLINE u32 get_paddr_ptag(u32 paddr) {
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return paddr >> 12;
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}
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void writeback_dcache(u64 vaddr, u32 paddr);
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u8 cache_read_byte(u64 vaddr, u32 paddr);
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void cache_write_byte(u64 vaddr, u32 paddr, u8 value);
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u16 cache_read_half(u64 vaddr, u32 paddr);
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void cache_write_half(u64 vaddr, u32 paddr, u16 value);
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u32 cache_read_word(u64 vaddr, u32 paddr);
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void cache_write_word(u64 vaddr, u32 paddr, u32 value);
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u64 cache_read_dword(u64 vaddr, u32 paddr);
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void cache_write_dword(u64 vaddr, u32 paddr, u64 value);
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#endif // N64_CACHE_H
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@ -1,5 +1,6 @@
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#include "fpu_instructions.h"
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#include <cache.h>
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#include <util.h>
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#include <mem/n64bus.h>
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#include <math.h>
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@ -1017,7 +1018,7 @@ MIPS_INSTR(mips_ldc1) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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u64 value = n64_read_physical_dword(physical);
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u64 value = conditional_cache_read_dword(cached, address, physical);
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set_fpu_register_dword_fr(instruction.i.rt, value);
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}
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}
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@ -1034,7 +1035,7 @@ MIPS_INSTR(mips_sdc1) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_STORE), 0);
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} else {
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n64_write_physical_dword(physical, value);
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conditional_cache_write_dword(cached, address, physical, value);
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}
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}
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@ -1049,7 +1050,7 @@ MIPS_INSTR(mips_lwc1) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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u32 value = n64_read_physical_word(physical);
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u32 value = conditional_cache_read_word(cached, address, physical);
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set_fpu_register_word_fr(instruction.fi.ft, value);
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}
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}
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@ -1066,7 +1067,7 @@ MIPS_INSTR(mips_swc1) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_STORE), 0);
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} else {
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n64_write_physical_word(physical, value);
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conditional_cache_write_word(cached, address, physical, value);
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}
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}
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@ -1,6 +1,7 @@
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#include "mips_instructions.h"
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#include "r4300i_register_access.h"
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#include <cache.h>
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#include <mem/n64bus.h>
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MIPS_INSTR(mips_nop) {}
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@ -104,7 +105,8 @@ MIPS_INSTR(mips_cache) {
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case DCACHE_OP(0): { // Index_Write_Back_Invalidate
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int cache_line = get_dcache_line_index(virtual_address);
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if (N64CPU.dcache[cache_line].valid) {
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logfatal("writeback");
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writeback_dcache(virtual_address, physical);
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N64CPU.dcache[cache_line].valid = false;
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}
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break;
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}
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@ -133,7 +135,7 @@ MIPS_INSTR(mips_cache) {
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case DCACHE_OP(4): {
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int cache_line = get_dcache_line_index(virtual_address);
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if (N64CPU.dcache[cache_line].valid && N64CPU.dcache[cache_line].ptag == physical_tag) {
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logfatal("Hit_Invalidate dcache unimplemented");
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N64CPU.dcache[cache_line].valid = false;
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}
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break;
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}
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@ -143,7 +145,8 @@ MIPS_INSTR(mips_cache) {
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case DCACHE_OP(5): { // Hit_Write_Back_Invalidate
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int cache_line = get_dcache_line_index(virtual_address);
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if (N64CPU.dcache[cache_line].valid && N64CPU.dcache[cache_line].ptag == physical_tag) {
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logfatal("Hit_Write_Back_Invalidate dcache unimplemented\n");
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writeback_dcache(virtual_address, physical);
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N64CPU.dcache[cache_line].valid = false;
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}
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break;
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}
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@ -153,7 +156,7 @@ MIPS_INSTR(mips_cache) {
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case DCACHE_OP(6): { // Hit_Write_Back dcache
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int cache_line = get_dcache_line_index(virtual_address);
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if (N64CPU.dcache[cache_line].valid && N64CPU.dcache[cache_line].ptag == physical_tag) {
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logfatal("Hit_Write_Back dcache unimplemented\n");
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writeback_dcache(virtual_address, physical);
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}
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break;
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}
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@ -239,7 +242,7 @@ MIPS_INSTR(mips_ld) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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u64 value = n64_read_physical_dword(physical);
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u64 value = conditional_cache_read_dword(cached, address, physical);
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set_register(instruction.i.rt, value);
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}
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}
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@ -263,7 +266,7 @@ MIPS_INSTR(mips_lbu) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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u8 value = n64_read_physical_byte(physical);
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u8 value = conditional_cache_read_byte(cached, address, physical);
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set_register(instruction.i.rt, value); // zero extend
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}
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}
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@ -282,7 +285,7 @@ MIPS_INSTR(mips_lhu) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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u16 value = n64_read_physical_half(physical);
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u16 value = conditional_cache_read_half(cached, address, physical);
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set_register(instruction.i.rt, value); // zero extend
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}
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}
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@ -300,7 +303,7 @@ MIPS_INSTR(mips_lh) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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s16 value = n64_read_physical_half(physical);
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s16 value = conditional_cache_read_half(cached, address, physical);
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set_register(instruction.i.rt, (s64)value); // zero extend
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}
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}
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@ -320,7 +323,7 @@ MIPS_INSTR(mips_lw) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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s32 value = n64_read_physical_word(physical);
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s32 value = conditional_cache_read_word(cached, address, physical);
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set_register(instruction.i.rt, (s64)value);
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}
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}
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@ -338,7 +341,7 @@ MIPS_INSTR(mips_lwu) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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u32 value = n64_read_physical_word(physical);
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u32 value = conditional_cache_read_word(cached, address, physical);
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set_register(instruction.i.rt, value);
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}
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}
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@ -355,7 +358,7 @@ MIPS_INSTR(mips_sb) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_STORE), 0);
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} else {
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n64_write_physical_byte(physical, value);
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conditional_cache_write_byte(cached, address, physical, value);
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}
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}
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@ -370,7 +373,7 @@ MIPS_INSTR(mips_sh) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_STORE), 0);
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} else {
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n64_write_physical_half(physical, value);
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conditional_cache_write_half(cached, address, physical, value);
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}
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}
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@ -391,7 +394,7 @@ MIPS_INSTR(mips_sw) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_STORE), 0);
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} else {
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n64_write_physical_word(physical, get_register(instruction.i.rt));
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conditional_cache_write_word(cached, address, physical, get_register(instruction.i.rt));
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}
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}
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@ -412,7 +415,7 @@ MIPS_INSTR(mips_sd) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_STORE), 0);
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} else {
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n64_write_physical_dword(physical, value);
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conditional_cache_write_dword(cached, address, physical, value);
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}
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}
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@ -441,7 +444,7 @@ MIPS_INSTR(mips_lb) {
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on_tlb_exception(address);
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r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
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} else {
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s8 value = n64_read_physical_byte(physical);
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s8 value = conditional_cache_read_byte(cached, address, physical);
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set_register(instruction.i.rt, (s64)value);
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}
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}
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@ -459,7 +462,7 @@ MIPS_INSTR(mips_lwl) {
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} else {
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u32 shift = 8 * ((address ^ 0) & 3);
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u32 mask = 0xFFFFFFFF << shift;
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u32 data = n64_read_physical_word(physical & ~3);
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u32 data = conditional_cache_read_word(cached, address & ~3, physical & ~3);
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s32 result = (get_register(instruction.i.rt) & ~mask) | data << shift;
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set_register(instruction.i.rt, (s64)result);
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}
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@ -477,7 +480,7 @@ MIPS_INSTR(mips_lwr) {
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u32 shift = 8 * ((address ^ 3) & 3);
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u32 mask = 0xFFFFFFFF >> shift;
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u32 data = n64_read_physical_word(physical & ~3);
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u32 data = conditional_cache_read_word(cached, address & ~3, physical & ~3);
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s32 result = (get_register(instruction.i.rt) & ~mask) | data >> shift;
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set_register(instruction.i.rt, (s64)result);
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}
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@ -495,9 +498,9 @@ MIPS_INSTR(mips_swl) {
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} else {
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u32 shift = 8 * ((address ^ 0) & 3);
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u32 mask = 0xFFFFFFFF >> shift;
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u32 data = n64_read_physical_word(physical & ~3);
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u32 data = conditional_cache_read_word(cached, address & ~3, physical & ~3);
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u32 oldreg = get_register(instruction.i.rt);
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n64_write_physical_word(physical & ~3, (data & ~mask) | (oldreg >> shift));
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conditional_cache_write_word(cached, address & ~3, physical & ~3, (data & ~mask) | (oldreg >> shift));
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}
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}
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@ -512,9 +515,9 @@ MIPS_INSTR(mips_swr) {
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} else {
|
||||
u32 shift = 8 * ((address ^ 3) & 3);
|
||||
u32 mask = 0xFFFFFFFF << shift;
|
||||
u32 data = n64_read_physical_word(physical & ~3);
|
||||
u32 data = conditional_cache_read_word(cached, address & ~3, physical & ~3);
|
||||
u32 oldreg = get_register(instruction.i.rt);
|
||||
n64_write_physical_word(physical & ~3, (data & ~mask) | oldreg << shift);
|
||||
conditional_cache_write_word(cached, address & ~3, physical & ~3, (data & ~mask) | oldreg << shift);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -529,7 +532,7 @@ MIPS_INSTR(mips_ldl) {
|
|||
} else {
|
||||
int shift = 8 * ((address ^ 0) & 7);
|
||||
u64 mask = (u64) 0xFFFFFFFFFFFFFFFF << shift;
|
||||
u64 data = n64_read_physical_dword(physical & ~7);
|
||||
u64 data = conditional_cache_read_dword(cached, address & ~7, physical & ~7);
|
||||
u64 oldreg = get_register(instruction.i.rt);
|
||||
|
||||
set_register(instruction.i.rt, (oldreg & ~mask) | (data << shift));
|
||||
|
|
@ -547,7 +550,7 @@ MIPS_INSTR(mips_ldr) {
|
|||
} else {
|
||||
int shift = 8 * ((address ^ 7) & 7);
|
||||
u64 mask = (u64) 0xFFFFFFFFFFFFFFFF >> shift;
|
||||
u64 data = n64_read_physical_dword(physical & ~7);
|
||||
u64 data = conditional_cache_read_dword(cached, address & ~7, physical & ~7);
|
||||
u64 oldreg = get_register(instruction.i.rt);
|
||||
|
||||
set_register(instruction.i.rt, (oldreg & ~mask) | (data >> shift));
|
||||
|
|
@ -567,9 +570,9 @@ MIPS_INSTR(mips_sdl) {
|
|||
int shift = 8 * ((address ^ 0) & 7);
|
||||
u64 mask = 0xFFFFFFFFFFFFFFFF;
|
||||
mask >>= shift;
|
||||
u64 data = n64_read_physical_dword(physical & ~7);
|
||||
u64 data = conditional_cache_read_dword(cached, address & ~7, physical & ~7);
|
||||
u64 oldreg = get_register(instruction.i.rt);
|
||||
n64_write_physical_dword(physical & ~7, (data & ~mask) | (oldreg >> shift));
|
||||
conditional_cache_write_dword(cached, address & ~7, physical & ~7, (data & ~mask) | (oldreg >> shift));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -585,9 +588,9 @@ MIPS_INSTR(mips_sdr) {
|
|||
int shift = 8 * ((address ^ 7) & 7);
|
||||
u64 mask = 0xFFFFFFFFFFFFFFFF;
|
||||
mask <<= shift;
|
||||
u64 data = n64_read_physical_dword(physical & ~7);
|
||||
u64 data = conditional_cache_read_dword(cached, address & ~7, physical & ~7);
|
||||
u64 oldreg = get_register(instruction.i.rt);
|
||||
n64_write_physical_dword(physical & ~7, (data & ~mask) | (oldreg << shift));
|
||||
conditional_cache_write_dword(cached, address & ~7, physical & ~7, (data & ~mask) | (oldreg << shift));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -602,7 +605,7 @@ MIPS_INSTR(mips_ll) {
|
|||
on_tlb_exception(address);
|
||||
r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
|
||||
} else {
|
||||
s32 result = n64_read_physical_word(physical);
|
||||
s32 result = conditional_cache_read_word(cached, address, physical);
|
||||
if ((address & 0b11) > 0) {
|
||||
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016" PRIX64, address);
|
||||
}
|
||||
|
|
@ -632,7 +635,7 @@ MIPS_INSTR(mips_lld) {
|
|||
on_tlb_exception(address);
|
||||
r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_LOAD), 0);
|
||||
} else {
|
||||
u64 result = n64_read_physical_dword(physical);
|
||||
u64 result = conditional_cache_read_dword(cached, address, physical);
|
||||
if ((address & 0b111) > 0) {
|
||||
logfatal("TODO: throw an 'address error' exception! Tried to load from unaligned address 0x%016" PRIX64, address);
|
||||
}
|
||||
|
|
@ -663,7 +666,7 @@ MIPS_INSTR(mips_sc) {
|
|||
r4300i_handle_exception(N64CPU.prev_pc, get_tlb_exception_code(N64CP0.tlb_error, BUS_STORE), 0);
|
||||
} else {
|
||||
u32 value = get_register(instruction.i.rt);
|
||||
n64_write_physical_word(physical_address, value);
|
||||
conditional_cache_write_word(cached, address, physical_address, value);
|
||||
set_register(instruction.i.rt, 1); // Success!
|
||||
}
|
||||
} else {
|
||||
|
|
@ -693,7 +696,7 @@ MIPS_INSTR(mips_scd) {
|
|||
u32 physical_address = resolve_virtual_address_or_die(address, BUS_STORE, &cached);
|
||||
|
||||
u64 value = get_register(instruction.i.rt);
|
||||
n64_write_physical_dword(physical_address, value);
|
||||
conditional_cache_write_dword(cached, address, physical_address, value);
|
||||
set_register(instruction.i.rt, 1); // Success!
|
||||
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
#ifndef N64_R4300I_H
|
||||
#define N64_R4300I_H
|
||||
#include <cpu/cache.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include <string.h>
|
||||
|
|
@ -621,44 +622,6 @@ typedef union fgr {
|
|||
|
||||
ASSERTDWORD(fgr_t);
|
||||
|
||||
typedef struct icache_line {
|
||||
struct {
|
||||
u32 valid:1;
|
||||
u32 ptag:20;
|
||||
};
|
||||
// since the icache will only ever be accessed as u32, just store it as u32
|
||||
u32 data[8]; // 32 bytes, 8 words
|
||||
} icache_line_t;
|
||||
|
||||
typedef struct dcache_line {
|
||||
struct {
|
||||
u32 valid:1;
|
||||
u32 dirty:1;
|
||||
u32 ptag:20;
|
||||
};
|
||||
u8 data[16];
|
||||
} dcache_line_t;
|
||||
|
||||
INLINE int get_icache_line_index(u64 vaddr) {
|
||||
return (vaddr >> 5) & 0x1FF;
|
||||
}
|
||||
|
||||
INLINE u32 get_icache_line_start(u32 paddr) {
|
||||
return paddr & ~0x1F;
|
||||
}
|
||||
|
||||
INLINE int get_dcache_line_index(u64 vaddr) {
|
||||
return (vaddr >> 4) & 0x1FF;
|
||||
}
|
||||
|
||||
INLINE u32 get_dcache_line_start(u32 paddr) {
|
||||
return paddr & ~0xF;
|
||||
}
|
||||
|
||||
INLINE u32 get_paddr_ptag(u32 paddr) {
|
||||
return paddr >> 13;
|
||||
}
|
||||
|
||||
typedef struct r4300i {
|
||||
u64 gpr[32];
|
||||
fgr_t f[32];
|
||||
|
|
|
|||
|
|
@ -161,10 +161,10 @@ INLINE resolve_virtual_address_handler get_resolve_virtual_address_handler() {
|
|||
|
||||
#define resolve_virtual_address(vaddr, bus_access, cached, physical) N64CP0.resolve_virtual_address(vaddr, bus_access, cached, physical)
|
||||
|
||||
INLINE u32 resolve_virtual_address_or_die(u64 virtual, bus_access_t bus_access, bool* cached) {
|
||||
INLINE u32 resolve_virtual_address_or_die(u64 vaddr, bus_access_t bus_access, bool* cached) {
|
||||
u32 physical;
|
||||
if (!resolve_virtual_address(virtual, bus_access, cached, &physical)) {
|
||||
logfatal("Unhandled TLB exception at 0x%016" PRIX64 "! Stop calling resolve_virtual_address_or_die() here!", virtual);
|
||||
if (!resolve_virtual_address(vaddr, bus_access, cached, &physical)) {
|
||||
logfatal("Unhandled TLB exception at 0x%016" PRIX64 "! Stop calling resolve_virtual_address_or_die() here!", vaddr);
|
||||
}
|
||||
return physical;
|
||||
}
|
||||
|
|
@ -183,7 +183,73 @@ u8 n64_read_physical_byte(u32 address);
|
|||
|
||||
INLINE u8 n64_read_byte(u64 address) {
|
||||
bool cached;
|
||||
return n64_read_physical_byte(resolve_virtual_address_or_die(address, false, &cached));
|
||||
return n64_read_physical_byte(resolve_virtual_address_or_die(address, BUS_LOAD, &cached));
|
||||
}
|
||||
|
||||
INLINE u8 conditional_cache_read_byte(bool cached, u64 vaddr, u32 paddr) {
|
||||
if (cached) {
|
||||
return cache_read_byte(vaddr, paddr);
|
||||
} else {
|
||||
return n64_read_physical_byte(paddr);
|
||||
}
|
||||
}
|
||||
|
||||
INLINE void conditional_cache_write_byte(bool cached, u64 vaddr, u32 paddr, u8 value) {
|
||||
if (cached) {
|
||||
cache_write_byte(vaddr, paddr, value);
|
||||
} else {
|
||||
n64_write_physical_byte(paddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
INLINE u16 conditional_cache_read_half(bool cached, u64 vaddr, u32 paddr) {
|
||||
if (cached) {
|
||||
return cache_read_half(vaddr, paddr);
|
||||
} else {
|
||||
return n64_read_physical_half(paddr);
|
||||
}
|
||||
}
|
||||
|
||||
INLINE void conditional_cache_write_half(bool cached, u64 vaddr, u32 paddr, u16 value) {
|
||||
if (cached) {
|
||||
cache_write_half(vaddr, paddr, value);
|
||||
} else {
|
||||
n64_write_physical_half(paddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
INLINE u32 conditional_cache_read_word(bool cached, u64 vaddr, u32 paddr) {
|
||||
if (cached) {
|
||||
return cache_read_word(vaddr, paddr);
|
||||
} else {
|
||||
return n64_read_physical_word(paddr);
|
||||
}
|
||||
}
|
||||
|
||||
INLINE void conditional_cache_write_word(bool cached, u64 vaddr, u32 paddr, u32 value) {
|
||||
if (cached) {
|
||||
cache_write_word(vaddr, paddr, value);
|
||||
} else {
|
||||
n64_write_physical_word(paddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
INLINE u64 conditional_cache_read_dword(bool cached, u64 vaddr, u32 paddr) {
|
||||
if (cached) {
|
||||
return cache_read_dword(vaddr, paddr);
|
||||
} else {
|
||||
return n64_read_physical_dword(paddr);
|
||||
}
|
||||
}
|
||||
|
||||
INLINE void conditional_cache_write_dword(bool cached, u64 vaddr, u32 paddr, u64 value) {
|
||||
if (cached) {
|
||||
cache_write_dword(vaddr, paddr, value);
|
||||
} else {
|
||||
n64_write_physical_dword(paddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
#endif //N64_N64BUS_H
|
||||
|
|
|
|||
|
|
@ -165,8 +165,8 @@ typedef struct softrdp_state {
|
|||
void softrdp_init(softrdp_state_t* state, uint8_t* rdramptr);
|
||||
#define full_sync_softrdp() do {} while(0)
|
||||
void softrdp_enqueue_command(softrdp_state_t* rdp, int command_length, uint64_t* buffer);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
Loading…
Reference in a new issue