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Add more details to EmulatedException.
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@ -2,4 +2,11 @@
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// EmulatedException interrupts processing of an instruction
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// and prevents state (such as memory or registers) being updated.
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export class EmulatedException {
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constructor(msg) {
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this.msg = msg;
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}
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toString() {
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return this.msg;
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}
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}
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14
src/r4300.js
14
src/r4300.js
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@ -1183,14 +1183,14 @@ export class CPU0 {
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const tlb = this.tlbFindEntry(address);
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if (!tlb) {
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this.raiseTLBException(UT_VEC, cpu0reg.causeExcCodeTLBL, address);
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throw new EmulatedException();
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throw new EmulatedException('TLBL UT_VEC');
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}
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const odd = address & tlb.checkbit;
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const entryLo = odd ? tlb.pfno : tlb.pfne;
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if ((entryLo & TLBLO_V) === 0) {
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this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeTLBL, address);
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throw new EmulatedException();
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throw new EmulatedException('TLBL E_VEC');
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}
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const phys = odd ? tlb.physOdd : tlb.physEven;
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@ -1202,18 +1202,18 @@ export class CPU0 {
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const tlb = this.tlbFindEntry(address);
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if (!tlb) {
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this.raiseTLBException(UT_VEC, cpu0reg.causeExcCodeTLBS, address);
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throw new EmulatedException();
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throw new EmulatedException('TLBS UT_VEC');
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}
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const odd = address & tlb.checkbit;
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const entryLo = odd ? tlb.pfno : tlb.pfne;
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if ((entryLo & TLBLO_V) === 0) {
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this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeTLBS, address);
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throw new EmulatedException();
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throw new EmulatedException('TLBS E_VEC');
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}
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if ((entryLo & TLBLO_D) === 0) {
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this.raiseTLBException(E_VEC, cpu0reg.causeExcCodeMod, address);
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throw new EmulatedException();
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throw new EmulatedException('Mod E_VEC');
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}
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const phys = odd ? tlb.physOdd : tlb.physEven;
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@ -1223,12 +1223,12 @@ export class CPU0 {
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unalignedLoad(address) {
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this.raiseAdELException(address);
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throw new EmulatedException();
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throw new EmulatedException('AdEL load');
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}
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unalignedStore(address) {
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this.raiseAdESException(address);
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throw new EmulatedException();
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throw new EmulatedException('AdES store');
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}
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execBreakpoint() {
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