mirror of
https://github.com/extremscorner/not64.git
synced 2024-05-29 01:07:58 -04:00
- Full TLB in ARAM for GC (-DARAM_TLBCACHE & TLB-Cache.c)
- GC ROM cache is ~3.93MB (63x64Kb blocks) in ARAM - Moved ARQ_Init and ARQ_Reset to ARAM_manager_init - TODO: revise ROM cache or possibly remove it from ARAM to L1
This commit is contained in:
emukidid
parent
7105989276
commit
aba3e986c1
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@ -8,7 +8,7 @@ CFLAGS = -g -O3 -Wall $(MACHDEP) $(INCLUDE) \
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-DCPU_SHUTDOWN -DSPC700_SHUTDOWN -DVAR_CYCLES -DSOUND \
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-DNOASM -DNGC -DNOASM -DPIXEL_FORMAT=RGB565 \
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-fno-exceptions -Wno-unused-parameter -pipe \
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-DUSE_GUI -DNGC -DHW_DOL -DGLN64_GX -DUSE_TLB_CACHE -DARAM_BLOCKCACHE \
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-DUSE_GUI -DNGC -DHW_DOL -DGLN64_GX -DUSE_TLB_CACHE -DARAM_BLOCKCACHE -DARAM_TLBCACHE \
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-DTHREADED_AUDIO -DUSE_RECOMP_CACHE -DPPC_DYNAREC -DFASTMEM -DRELEASE -DMENU_V2\
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#-DSHOW_DEBUG #-DUSE_TLB_CACHE \
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#-DPPC_DYNAREC -DNO_BT -DPROFILE #-DSHOW_DEBUG #-DDEBUGON #-DPRINTGECKO
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@ -75,7 +75,7 @@ OBJ =main/rom_gc.o \
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r4300/ARAM-blocks.o \
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r4300/Recomp-Cache-Heap.o \
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gc_memory/tlb.o \
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gc_memory/TLB-Cache-hash.o \
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gc_memory/TLB-Cache.o \
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gc_memory/memory.o \
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gc_memory/ARAM.o \
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gc_memory/dma.o \
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@ -24,6 +24,7 @@
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#include <malloc.h>
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#include <stdio.h>
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#include <ogc/aram.h>
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#include <ogc/arqueue.h>
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#include "ARAM.h"
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typedef struct {
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@ -42,8 +43,9 @@ static int initialized=0;
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AR_GetSize() == 16,777,216 bytes
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bytes type
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1. 16,384 DSP reserved
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2. 245,760 empty
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3. 12,320,768 ROM cache (47*256kb blocks)
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2. 49,152 empty
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3. 4,128,768 ROM cache (63*64kb blocks)
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3. 8,388,608 TLB LUTs
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4. 4,194,304 blocks (dynarec)
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*/
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@ -52,9 +54,9 @@ void ARAM_manager_init(void){
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AR_Init(NULL, 0);
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max_blocks = (AR_GetSize() - (256*1024) - (4*1024*1024))/BLOCK_SIZE;
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max_blocks = (AR_GetSize() - (64*1024) - (4*1024*1024) - (8*1024*1024))/BLOCK_SIZE;
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ARAM_blocks = malloc(max_blocks * sizeof(ARAM_block));
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int i, addr = 256*1024;
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int i, addr = 64*1024;
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for(i=0; i<max_blocks; ++i){
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ARAM_blocks[i].valid = FALSE;
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ARAM_blocks[i].addr = addr;
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@ -65,6 +67,8 @@ void ARAM_manager_init(void){
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alloced_blocks = 0;
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initialized = 1;
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ARQ_Reset();
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ARQ_Init();
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}
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void ARAM_manager_deinit(void){
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@ -24,7 +24,7 @@
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#ifndef ARAM_H
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#define ARAM_H
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#define BLOCK_SIZE (256*1024)
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#define BLOCK_SIZE (64*1024)
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void ARAM_manager_init(void);
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void ARAM_manager_deinit(void);
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@ -1,5 +1,5 @@
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/**
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* Wii64 - TLB-Cache-hash.c
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* Wii64 - TLB-Cache-hash.c (Deprecated)
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* Copyright (C) 2007, 2008, 2009 Mike Slegeir
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* Copyright (C) 2007, 2008, 2009 emu_kidid
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*
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@ -1,11 +1,13 @@
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/**
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* Wii64 - TLB-Cache.c (Deprecated)
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* Copyright (C) 2007, 2008, 2009 emu_kidid
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* Copyright (C) 2007, 2008, 2009 Mike Slegeir
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*
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* This is how the TLB LUT should be accessed, this way it won't waste RAM
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* This is how the TLB LUT should be accessed, this way it won't waste RAM, but ARAM
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*
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* Wii64 homepage: http://www.emulatemii.com
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* email address: tehpola@gmail.com
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* email address: emukidid@gmail.com
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*
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*
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* This program is free software; you can redistribute it and/
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@ -20,81 +22,138 @@
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*
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**/
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/*
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FIXME: The DMA transfers seem to overflow small buffers
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*/
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#ifdef ARAM_TLBCACHE
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#include <ogc/arqueue.h>
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#include <gccore.h>
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#include <stdlib.h>
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#include <malloc.h>
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#include <string.h>
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#include <stdio.h>
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#include "ARAM.h"
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#include "TLB-Cache.h"
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#include "../gui/DEBUG.h"
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static ARQRequest ARQ_request_TLB;
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#define TLB_W_TYPE 0
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#define TLB_R_TYPE 1
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#define TLB_W_CACHE_ADDR 0x400000
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#define TLB_R_CACHE_ADDR 0x800000
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#define CACHED_TLB_ENTRIES 1024
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#define CACHED_TLB_SIZE CACHED_TLB_ENTRIES * 4
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//TLB LUT W
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unsigned long tlb_w_block[CACHED_TLB_ENTRIES] __attribute__((aligned(32))); //last 4kb chunk of ptrs pulled
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static u32 tlb_w_dirty = 0;
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static u32 tlb_w_last_addr = 0;
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//TLB LUT R
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unsigned long tlb_r_block[CACHED_TLB_ENTRIES] __attribute__((aligned(32))); //last 4kb chunk of ptrs pulled
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static u32 tlb_r_dirty = 0;
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static u32 tlb_r_last_addr = 0;
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static int* TLB_LUT_r, * TLB_LUT_w;
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// We must moved 32-byte aligned, 32 byte chunks of the TLB
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static unsigned int value[8] __attribute__((aligned(32)));
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static ARQRequest ARQ_request;
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void TLBCache_init(void){
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ARQ_Init();
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// FIXME: I'm going to assume that nothings in the ARAM yet
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ARAM_block_alloc_contiguous(&TLB_LUT_r, 'T', 4);
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ARAM_block_alloc_contiguous(&TLB_LUT_w, 'T', 4);
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// Zero out the LUTs
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int chunkSize = ARQ_GetChunkSize(), offset = 0;
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char* zeroes = memalign(32, chunkSize);
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memset(zeroes, 0, chunkSize);
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DCFlushRange(zeroes, chunkSize);
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while(offset < 4 * 1024 * 1024){
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ARQ_PostRequest(&ARQ_request, 0x0, AR_MRAMTOARAM, ARQ_PRIO_HI,
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TLB_LUT_r + offset, zeroes, chunkSize);
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ARQ_PostRequest(&ARQ_request, 0x0, AR_MRAMTOARAM, ARQ_PRIO_HI,
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TLB_LUT_w + offset, zeroes, chunkSize);
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offset += chunkSize;
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int i = 0;
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for(i=0;i<0x100000;i++) {
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TLBCache_set_w(i,0);
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TLBCache_set_r(i,0);
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}
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free(zeroes);
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}
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void TLBCache_deinit(void){
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ARAM_block_free_contiguous(&TLB_LUT_r, 4);
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ARAM_block_free_contiguous(&TLB_LUT_w, 4);
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TLBCache_init();
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}
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unsigned int inline TLBCache_get_r(unsigned int page){
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//printf("TLBCache_get_r(%08x)\n", page);
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DCInvalidateRange(value, 32);
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ARQ_PostRequest(&ARQ_request, 0x718, AR_ARAMTOMRAM, ARQ_PRIO_LO,
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TLB_LUT_r + (page&(~0x7)), value, 32);
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return value[page&0x7];
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unsigned int TLBCache_get_r(unsigned int page){
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int block_byte_address = ((page - (page % CACHED_TLB_ENTRIES)) * 4);
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if(block_byte_address != tlb_r_last_addr) { //if addr isn't in the last block
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if(tlb_r_dirty) { //current chunk needs to be written back to ARAM
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ARAM_WriteTLBBlock(tlb_r_last_addr, TLB_R_TYPE);
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tlb_r_dirty=0;
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}
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ARAM_ReadTLBBlock(block_byte_address, TLB_R_TYPE); //read the block the addr we want lies in (aligned to 4kb)
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tlb_r_last_addr = block_byte_address; //the start of this block
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}
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return tlb_r_block[(page % CACHED_TLB_ENTRIES)];
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}
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unsigned int inline TLBCache_get_w(unsigned int page){
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//printf("TLBCache_get_w(%08x)\n", page);
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DCInvalidateRange(value, 32);
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ARQ_PostRequest(&ARQ_request, 0x718, AR_ARAMTOMRAM, ARQ_PRIO_LO,
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TLB_LUT_w + (page&(~0x7)), value, 32);
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return value[page&0x7];
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unsigned int TLBCache_get_w(unsigned int page){
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int block_byte_address = ((page - (page % CACHED_TLB_ENTRIES)) * 4);
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if(block_byte_address != tlb_w_last_addr) { //if addr isn't in the last block
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if(tlb_w_dirty) { //current chunk needs to be written back to ARAM
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ARAM_WriteTLBBlock(tlb_w_last_addr, TLB_W_TYPE);
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tlb_w_dirty=0;
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}
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ARAM_ReadTLBBlock(block_byte_address, TLB_W_TYPE); //read the block the addr we want lies in (aligned to 4kb)
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tlb_w_last_addr = block_byte_address; //the start of this block
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}
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return tlb_w_block[(page % CACHED_TLB_ENTRIES)];
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}
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void inline TLBCache_set_r(unsigned int page, unsigned int val){
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//printf("TLBCache_set_r(%08x, %08x)\n", page, val);
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DCInvalidateRange(value, 32);
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ARQ_PostRequest(&ARQ_request, 0x718, AR_ARAMTOMRAM, ARQ_PRIO_LO,
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TLB_LUT_r + (page&(~0x7)), value, 32);
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value[page&0x7] = val;
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DCFlushRange(value, 32);
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ARQ_PostRequest(&ARQ_request, 0x718, AR_MRAMTOARAM, ARQ_PRIO_LO,
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TLB_LUT_r + (page&(~0x7)), value, 32);
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void TLBCache_set_r(unsigned int page, unsigned int val){
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int block_byte_address = ((page - (page % CACHED_TLB_ENTRIES)) * 4);
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if(block_byte_address != tlb_r_last_addr) { //the block we want to write to is not cached
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ARAM_WriteTLBBlock(tlb_r_last_addr, TLB_R_TYPE); //we need to put the current chunk back into ARAM and pull out another
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ARAM_ReadTLBBlock(block_byte_address, TLB_R_TYPE); //read the block the addr we want lies in (aligned to 4kb)
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tlb_r_last_addr = block_byte_address; //the start of this block
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}
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tlb_r_block[(page % CACHED_TLB_ENTRIES)] = val; //set the value
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tlb_r_dirty=1; // this block, although new, is dirty from now
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}
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void inline TLBCache_set_w(unsigned int page, unsigned int val){
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//printf("TLBCache_set_w(%08x, %08x)\n", page, val);
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DCInvalidateRange(value, 32);
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ARQ_PostRequest(&ARQ_request, 0x718, AR_ARAMTOMRAM, ARQ_PRIO_LO,
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TLB_LUT_w + (page&(~0x7)), value, 32);
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value[page&0x7] = val;
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DCFlushRange(value, 32);
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ARQ_PostRequest(&ARQ_request, 0x718, AR_MRAMTOARAM, ARQ_PRIO_LO,
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TLB_LUT_w + (page&(~0x7)), value, 32);
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void TLBCache_set_w(unsigned int page, unsigned int val){
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int block_byte_address = ((page - (page % CACHED_TLB_ENTRIES)) * 4);
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if(block_byte_address != tlb_w_last_addr) { //the block we want to write to is not cached
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ARAM_WriteTLBBlock(tlb_w_last_addr, TLB_W_TYPE); //we need to put the current chunk back into ARAM and pull out another
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ARAM_ReadTLBBlock(block_byte_address, TLB_W_TYPE); //read the block the addr we want lies in (aligned to 4kb)
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tlb_w_last_addr = block_byte_address; //the start of this block
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}
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tlb_w_block[(page % CACHED_TLB_ENTRIES)] = val; //set the value
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tlb_w_dirty=1; // this block, although new, is dirty from now
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}
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void TLBCache_dump_w(gzFile *f) {
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int i = 0;
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for(i=0;i<0x100000;i++) {
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unsigned long val = TLBCache_get_w(i);
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gzwrite(f, &val, sizeof(unsigned long));
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}
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}
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void TLBCache_dump_r(gzFile *f) {
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int i = 0;
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for(i=0;i<0x100000;i++) {
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unsigned long val = TLBCache_get_r(i);
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gzwrite(f, &val, sizeof(unsigned long));
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}
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}
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//addr == addr of 4kb block of PowerPC_block ptrs to pull out from ARAM
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void ARAM_ReadTLBBlock(u32 addr, int type)
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{
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int base_addr = (type == TLB_W_TYPE) ? TLB_W_CACHE_ADDR : TLB_R_CACHE_ADDR;
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int dest_addr = (type == TLB_W_TYPE) ? (int)&tlb_w_block[0] : (int)&tlb_r_block[0];
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ARQ_PostRequest(&ARQ_request_TLB, 0x2EAD, AR_ARAMTOMRAM, ARQ_PRIO_LO,
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(int)(base_addr + addr), dest_addr, CACHED_TLB_SIZE);
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DCInvalidateRange((void*)dest_addr, CACHED_TLB_SIZE);
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}
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//addr == addr of 4kb block of PowerPC_block ptrs to pull out from ARAM
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void ARAM_WriteTLBBlock(u32 addr, int type)
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{
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int base_addr = (type == TLB_W_TYPE) ? TLB_W_CACHE_ADDR : TLB_R_CACHE_ADDR;
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int dest_addr = (type == TLB_W_TYPE) ? (int)&tlb_w_block[0] : (int)&tlb_r_block[0];
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DCFlushRange((void*)dest_addr, CACHED_TLB_SIZE);
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ARQ_PostRequest(&ARQ_request_TLB, 0x10AD, AR_MRAMTOARAM, ARQ_PRIO_HI,
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(int)(base_addr + addr), dest_addr, CACHED_TLB_SIZE);
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}
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#endif
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@ -54,6 +54,9 @@ void inline TLBCache_set_w(unsigned int page, unsigned int val);
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void TLBCache_dump_r(gzFile *f);
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void TLBCache_dump_w(gzFile *f);
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void ARAM_ReadTLBBlock(unsigned int addr, int type);
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void ARAM_WriteTLBBlock(unsigned int addr, int type);
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#endif
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#endif
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@ -54,7 +54,7 @@ void LoadingBar_showBar(float percent, const char* string);
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#define BLOCK_MASK (BLOCK_SIZE-1)
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#define OFFSET_MASK (0xFFFFFFFF-BLOCK_MASK)
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#define BLOCK_SHIFT (18) //only change ME and BLOCK_SIZE in gc_memory/aram.h
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#define BLOCK_SHIFT (16) //only change ME and BLOCK_SIZE in gc_memory/aram.h
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#define MAX_ROMSIZE (64*1024*1024)
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#define NUM_BLOCKS (MAX_ROMSIZE/BLOCK_SIZE)
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@ -68,14 +68,14 @@ static char readBefore = 0;
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#define L1_BLOCK_SIZE (4*1024) //63 * 4kb = ~256kb
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#define L1_BLOCK_MASK (L1_BLOCK_SIZE-1)
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#define L1_BLOCK_SHIFT (12)
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#define L1_NUM_BLOCKS (63) //16368kb / 256kb = 63
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#define L1_NUM_BLOCKS (8) //16368kb / 256kb = 63
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static u8 L1[L1_NUM_BLOCKS][L1_BLOCK_SIZE];
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static int L1tag[L1_NUM_BLOCKS];
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static u32 L1LRU[L1_NUM_BLOCKS];
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static u32 nextL1LRUValue;
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#endif
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ARQRequest ARQ_request;
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static ARQRequest ARQ_request_ROM;
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extern void showLoadProgress(float progress);
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extern void pauseAudio(void);
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extern void resumeAudio(void);
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@ -83,8 +83,6 @@ extern BOOL hasLoadedROM;
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void ROMCache_init(fileBrowser_file* file){
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readBefore = 0; //de-init byteswapping
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ARQ_Reset();
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ARQ_Init();
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ROM_too_big = (file->size) > (ARAM_block_available_contiguous() * BLOCK_SIZE);
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ROM_size = (file->size);
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#ifdef USE_ROM_CACHE_L1
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@ -119,7 +117,7 @@ static void inline ROMCache_load_block(char* block, int rom_offset){
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bytes_read = romFile_readFile(ROM_file, buffer, bytes_to_read);
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byte_swap(buffer, bytes_read);
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DCFlushRange(buffer, bytes_read);
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ARQ_PostRequest(&ARQ_request, 0x10AD, ARQ_MRAMTOARAM, ARQ_PRIO_HI,
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ARQ_PostRequest(&ARQ_request_ROM, 0x10AD, ARQ_MRAMTOARAM, ARQ_PRIO_HI,
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block + offset, buffer, bytes_read);
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offset += bytes_read;
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@ -153,7 +151,7 @@ void ARAM_ReadFromBlock(char *block,int startOffset, int bytes, char *dest)
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char* buffer = memalign(32,bytes);
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ARQ_PostRequest(&ARQ_request, 0x2EAD, AR_ARAMTOMRAM, ARQ_PRIO_LO,
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ARQ_PostRequest(&ARQ_request_ROM, 0x2EAD, AR_ARAMTOMRAM, ARQ_PRIO_LO,
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block + startOffset, buffer, bytes);
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DCInvalidateRange(buffer, bytes);
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memcpy(dest, buffer+(originalStartOffset%32), originalBytes);
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@ -256,7 +254,7 @@ int ROMCache_load(fileBrowser_file* file){
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}
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byte_swap((char*)buffer, bytes_read);
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DCFlushRange(buffer, bytes_read);
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ARQ_PostRequest(&ARQ_request, 0x10AD, AR_MRAMTOARAM, ARQ_PRIO_HI,
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ARQ_PostRequest(&ARQ_request_ROM, 0x10AD, AR_MRAMTOARAM, ARQ_PRIO_HI,
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block + offset, buffer, bytes_read);
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offset += bytes_read;
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@ -290,7 +288,7 @@ int ROMCache_load(fileBrowser_file* file){
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|||
}
|
||||
byte_swap((char*)buffer, bytes_read);
|
||||
DCFlushRange(buffer, bytes_read);
|
||||
ARQ_PostRequest(&ARQ_request, 0x10AD, AR_MRAMTOARAM, ARQ_PRIO_HI,
|
||||
ARQ_PostRequest(&ARQ_request_ROM, 0x10AD, AR_MRAMTOARAM, ARQ_PRIO_HI,
|
||||
ROM + offset, buffer, bytes_read);
|
||||
offset += bytes_read;
|
||||
|
||||
|
|
|
|||
|
|
@ -31,12 +31,12 @@
|
|||
#include "ARAM-blocks.h"
|
||||
#include "../gui/DEBUG.h"
|
||||
|
||||
extern ARQRequest ARQ_request;
|
||||
static ARQRequest ARQ_request_blocks;
|
||||
|
||||
#define BLOCKS_CACHE_ADDR 0xC00000
|
||||
#define CACHED_BLOCK_ENTRIES 1024
|
||||
#define CACHED_BLOCK_SIZE CACHED_BLOCK_ENTRIES * 4
|
||||
PowerPC_block* cached_block[CACHED_BLOCK_SIZE/sizeof(PowerPC_block*)] __attribute__((aligned(32))); //last 4kb chunk of ptrs pulled
|
||||
PowerPC_block* cached_block[CACHED_BLOCK_ENTRIES] __attribute__((aligned(32))); //last 4kb chunk of ptrs pulled
|
||||
static u32 cached_dirty = 0;
|
||||
static u32 cached_last_addr = 0;
|
||||
|
||||
|
|
@ -69,7 +69,7 @@ void blocks_set(u32 addr, PowerPC_block* ptr){
|
|||
//addr == addr of 4kb block of PowerPC_block ptrs to pull out from ARAM
|
||||
void ARAM_ReadBlock(u32 addr)
|
||||
{
|
||||
ARQ_PostRequest(&ARQ_request, 0x2EAD, AR_ARAMTOMRAM, ARQ_PRIO_LO,
|
||||
ARQ_PostRequest(&ARQ_request_blocks, 0x2EAD, AR_ARAMTOMRAM, ARQ_PRIO_LO,
|
||||
(int)(BLOCKS_CACHE_ADDR + addr), (int)&cached_block[0], CACHED_BLOCK_SIZE);
|
||||
DCInvalidateRange((void*)&cached_block, CACHED_BLOCK_SIZE);
|
||||
}
|
||||
|
|
@ -78,7 +78,7 @@ void ARAM_ReadBlock(u32 addr)
|
|||
void ARAM_WriteBlock(u32 addr)
|
||||
{
|
||||
DCFlushRange((void*)&cached_block, CACHED_BLOCK_SIZE);
|
||||
ARQ_PostRequest(&ARQ_request, 0x10AD, AR_MRAMTOARAM, ARQ_PRIO_HI,
|
||||
ARQ_PostRequest(&ARQ_request_blocks, 0x10AD, AR_MRAMTOARAM, ARQ_PRIO_HI,
|
||||
(int)(BLOCKS_CACHE_ADDR + addr), (int)&cached_block[0], CACHED_BLOCK_SIZE);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue