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Extracted RSX MMIO regs from @3141card's LV1 RE
This commit is contained in:
Alexandro Sánchez Bach
parent
690a867a2c
commit
1a864205dc
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@ -8,9 +8,9 @@ The PlayStation 3 GPU is the *Reality Synthesizer* (**RSX**), designed by Sony a
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* Lots of tests in the [PS3 Autotests](https://github.com/AlexAltea/ps3autotests/tree/master/tests/gpu) repository.
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* [Nouveau](http://nouveau.freedesktop.org/wiki/) open source drivers and information, specially [envytools](https://github.com/envytools/envytools/)
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Accurantly emulating RSX results in heavy performance drops. Furthermore, these measures are not required for the vast majority of applications available for the PlayStation 3. For that matter, the following RSX emulation modes exist in Nucleus that will be referred to throughout this document:
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Accurately emulating RSX results in heavy performance drops. Furthermore, these measures are not required for the vast majority of applications available for the PlayStation 3. For that matter, the following RSX emulation modes exist in Nucleus that will be referred to throughout this document:
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* __Accurate Emulation__ (*AE*): Worse performance. Compatibility with any hypervisor, regardless of HLE or LLE.
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* __Accurate Emulation__ (*AE*): Poor performance. Compatibility with any hypervisor, regardless of HLE or LLE.
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* __Fast Emulation__ (*FE*): Good performance. Compatibility user-mode applications compiled with the SCEI PS3 SDK, running on top of CellOS-LV1 HLE or CellOS-LV2 HLE.
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## Memory
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@ -56,11 +56,11 @@ TODO: Verify this.
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|----------|--------------------------------|
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| `0x0000` | NV01_NULL |
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| `0x0039` | NV03_MEMORY_TO_MEMORY_FORMAT |
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| `0x3062` | NV30_CONTEXT_SURFACES_2D |
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| `0x309E` | NV30_CONTEXT_SURFACE_SWIZZLED |
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| `0x308A` | NV30_IMAGE_FROM_CPU |
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| `0x3089` | NV30_SCALED_IMAGE_FROM_MEMORY |
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| `0x4097` | NV40_CURIE_PRIMITIVE |
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| `0x3062` | NV30_CONTEXT_SURFACES_2D |
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| `0x309E` | NV30_CONTEXT_SURFACE_SWIZZLED |
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| `0x308A` | NV30_IMAGE_FROM_CPU |
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| `0x3089` | NV30_SCALED_IMAGE_FROM_MEMORY |
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| `0x4097` | NV40_CURIE_PRIMITIVE |
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## VRAM
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@ -32,6 +32,7 @@
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<ClInclude Include="$(MSBuildThisFileDirectory)rsx\rsx_enum.h" />
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<ClInclude Include="$(MSBuildThisFileDirectory)rsx\rsx_fp.h" />
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<ClInclude Include="$(MSBuildThisFileDirectory)rsx\rsx_methods.h" />
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<ClInclude Include="$(MSBuildThisFileDirectory)rsx\rsx_mmio.h" />
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<ClInclude Include="$(MSBuildThisFileDirectory)rsx\rsx_pgraph.h" />
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<ClInclude Include="$(MSBuildThisFileDirectory)rsx\rsx_texture.h" />
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<ClInclude Include="$(MSBuildThisFileDirectory)rsx\rsx_vp.h" />
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@ -39,6 +39,9 @@
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</ClInclude>
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<ClInclude Include="$(MSBuildThisFileDirectory)list.h" />
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<ClInclude Include="$(MSBuildThisFileDirectory)gpu_hash.h" />
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<ClInclude Include="$(MSBuildThisFileDirectory)rsx\rsx_mmio.h">
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<Filter>rsx</Filter>
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</ClInclude>
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="$(MSBuildThisFileDirectory)rsx\rsx_pgraph.cpp">
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285
nucleus/gpu/rsx/rsx_mmio.h
Normal file
285
nucleus/gpu/rsx/rsx_mmio.h
Normal file
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@ -0,0 +1,285 @@
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/**
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* (c) 2014-2016 Alexandro Sanchez Bach. All rights reserved.
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* Released under GPL v2 license. Read LICENSE for more details.
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*/
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#pragma once
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#include "nucleus/common.h"
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/**
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* RSX MMIO
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* ========
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* The following offsets point into the 32 MB MMIO register space available at BAR0.
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* The entirety BAR0 or ranges of it can be mapped into virtual address space through the
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* `sys_rsx_device_map` CellOS-LV2 syscall, which relies on the
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* `lv1_gpu_device_map` CellOS-LV1 syscall.
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*
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* Each of the MMIO register ranges mappable by these syscalls correspond to different
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* "devices" (SCEI nomenclature) or "engines" (Nouveau nomenclature).
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*
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* The following table lists accessible RSX devices:
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* +------------+-------------------+--------------+
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* | Offset | Size | Device |
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* |------------|-------------------|--------------|
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* | 0x00002000 | 0x0002000 (8 KB) | PFIFO |
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* | 0x0000A000 | 0x0001000 (4 KB) | PCOUNTER |
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* | 0x00080100 | 0x0008000 (32 KB) | ? |
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* | 0x00088000 | 0x0001000 (4 KB) | PPCI |
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* | 0x0008A000 | 0x0001000 (4 KB) | ? |
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* | 0x00090000 | 0x0001000 (4 KB) | PFIFO_CACHE? |
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* | 0x00100000 | 0x0001000 (4 KB) | PFB |
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* | 0x00200000 | 0x0001000 (4 KB) | PMEDIA? |
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* | 0x00400000 | 0x0008000 (32 KB) | PGRAPH |
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* | 0x00600000 | 0x0010000 (64 KB) | PCRTC? |
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* +------------+-------------------+--------------+
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*/
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// PFIFO
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#define RSX_PFIFO_DELAY_0 0x00002040
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#define RSX_PFIFO_DMA_TIMESLICE 0x00002044
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#define RSX_PFIFO_UNK2048 0x00002048
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#define RSX_PFIFO_NEXT_CHANNEL 0x00002050
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#define RSX_PFIFO_UNK2054 0x00002054
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#define RSX_PFIFO_UNK2058 0x00002058 // NV36 Ch DMA
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#define RSX_PFIFO_UNK2088 0x00002088
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#define RSX_PFIFO_INTR_0 0x00002100 // TODO: Do the fields below match RSX_PFIFO_INTR_EN_0's ones due to a mistake?
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#define RSX_PFIFO_INTR_0_ACQUIRE_TIMEOUT // [06:06], 1(intr acquire timeout)
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#define RSX_PFIFO_INTR_0_FBI_STATE_TIMEOUT // [08:08], 1(intr FBI state timeout)
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#define RSX_PFIFO_INTR_0_FBI_READ_TIMEOUT // [09:09], 1(intr FBI read timeout)
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#define RSX_PFIFO_INTR_0_BIT10 // [10:10], ?
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#define RSX_PFIFO_INTR_0_DMA_PUT // [11:11], 1(intr DMA PUT)
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#define RSX_PFIFO_INTR_0_MARKER_ERROR // [12:12], 1(marker error)
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#define RSX_PFIFO_INTR_0_DMA_PUSHER // [18:18], 1(intr DMA pusher)
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#define RSX_PFIFO_INTR_0_RUNOUT_OVERFLOW // [22:22], 1(intr runout overflow)
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#define RSX_PFIFO_INTR_EN_0 0x00002140
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#define NV_PFIFO_INTR_CACHE_ERROR (1 << 0)
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#define NV_PFIFO_INTR_RUNOUT (1 << 4)
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#define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1 << 8)
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#define NV_PFIFO_INTR_DMA_PUSHER (1 << 12)
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#define NV_PFIFO_INTR_DMA_PT (1 << 16)
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#define NV_PFIFO_INTR_SEMAPHORE (1 << 20)
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#define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1 << 24)
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#define RSX_PFIFO_RAMHT 0x00002210
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#define RSX_PFIFO_RAMFC 0x00002214
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#define RSX_PFIFO_RAMRO 0x00002218
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#define RSX_PFIFO_UNK221C 0x0000221C
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#define RSX_PFIFO_RAMFC 0x00002220
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#define RSX_PFIFO_UNK2224 0x00002224
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#define RSX_PFIFO_UNK2228 0x00002228
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#define RSX_PFIFO_UNK222C 0x0000222C
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#define RSX_PFIFO_UNK2230 0x00002230
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#define RSX_PFIFO_UNK2410 0x00002410
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#define RSX_PFIFO_UNK2420 0x00002420
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#define RSX_PFIFO_CACHES 0x00002500
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#define RSX_PFIFO_MODE 0x00002504
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#define RSX_PFIFO_DMA 0x00002508
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#define RSX_PFIFO_SIZE 0x0000250C // LV1 does weird things here
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// TODO: Every word from 0x2510 to 0x254C is set to 0 on LV1
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#define RSX_PFIFO_CACHE1_PUSH0 0x00003200
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#define RSX_PFIFO_CACHE1_PUSH1 0x00003204 // TODO: Check CHID mask
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#define RSX_PFIFO_CACHE1_PUT 0x00003210
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#define RSX_PFIFO_CACHE1_DMA_PUSH 0x00003220
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#define RSX_PFIFO_CACHE1_DMA_FETCH 0x00003224
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_MASK 0x000000FF
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
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#define RSX_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_MASK 0x0000E000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000
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#define RSX_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000
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#define RSX_PFIFO_CACHE1_ENDIAN 0x80000000
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#define RSX_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF
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#define RSX_PFIFO_CACHE1_BIG_ENDIAN 0x80000000
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#define RSX_PFIFO_CACHE1_DMA_STATE 0x00003228
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#define RSX_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c
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#define RSX_PFIFO_CACHE1_DMA_CTL 0x00003230
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#define RSX_PFIFO_CACHE1_DMA_PUT 0x00003240
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#define RSX_PFIFO_CACHE1_DMA_GET 0x00003244
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#define RSX_PFIFO_CACHE1_REF_CNT 0x00003248
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#define RSX_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C
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#define RSX_PFIFO_CACHE1_PULL0 0x00003250 // TODO: Why doesn't the fields below exactly match LV1 ones?
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#define RSX_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010
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#define RSX_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000
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#define RSX_PFIFO_CACHE1_PULL0_BIT14 // [14:14], acquire: 0(idle), 1(busy)
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#define RSX_PFIFO_CACHE1_PULL0_BIT18 // [18:18], state: 0(idle), 1(busy)
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#define RSX_PFIFO_CACHE1_PULL0_BIT19 // [19:19],
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#define RSX_PFIFO_CACHE1_PULL0_BIT22 // [22:22], device: 0(s/w), 1(h/w)
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#define RSX_PFIFO_CACHE1_PULL0_BIT26 // [26:26], hash: 0(succeeded), 1(failed)
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#define RSX_PFIFO_CACHE1_PULL0_BIT30 // [30:30], access: 0(disable), 1(enable)
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#define RSX_PFIFO_CACHE1_PULL0_BIT31 // [31:31], fifo unset on init
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#define RSX_PFIFO_CACHE1_PULL1 0x00003254
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#define RSX_PFIFO_CACHE1_HASH 0x00003258
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#define RSX_PFIFO_CACHE1_UNK325C 0x0000325C
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#define RSX_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260
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#define RSX_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264
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#define RSX_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268
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#define RSX_PFIFO_CACHE1_SEMAPHORE 0x0000326C
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#define RSX_PFIFO_CACHE1_GET 0x00003270
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#define RSX_PFIFO_CACHE1_ENGINE 0x00003280
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#define RSX_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0
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#define RSX_PFIFO_GRCTX_INSTANCE 0x000032E0
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#define RSX_PFIFO_UNK32E4 0x000032E4
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#define RSX_PFIFO_UNK32E8 0x000032E8
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#define RSX_PFIFO_UNK3304 0x00003304
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// PFB
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#define RSX_PFB_BOOT_0 (0x00100000)
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#define RSX_PFB_BOOT_0_RAM_AMOUNT 0x00000003
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#define RSX_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
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#define RSX_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
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#define RSX_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
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#define RSX_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
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#define RSX_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
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#define RSX_PFB_BOOT_0_RAM_TYPE 0x00000028
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#define RSX_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
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#define RSX_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
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#define RSX_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010
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#define RSX_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018
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#define RSX_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020
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#define RSX_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028
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#define RSX_PFB_BOOT_0_UMA_ENABLE 0x00000100
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#define RSX_PFB_BOOT_0_UMA_SIZE 0x0000F000
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#define RSX_PFB_DEBUG_0 (0x00100080)
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#define RSX_PFB_DEBUG_0_PAGE_MODE 0x00000001
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#define RSX_PFB_DEBUG_0_REFRESH_OFF 0x00000010
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#define RSX_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003F00
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#define RSX_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x00004000
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#define RSX_PFB_DEBUG_0_SAFE_MODE 0x00008000
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#define RSX_PFB_DEBUG_0_ALOM_ENABLE 0x00010000
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#define RSX_PFB_DEBUG_0_CASOE 0x00100000
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#define RSX_PFB_DEBUG_0_CKE_INVERT 0x10000000
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#define RSX_PFB_DEBUG_0_REFINC 0x20000000
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#define RSX_PFB_DEBUG_0_SAVE_POWER_OFF 0x40000000
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#define RSX_PFB_UNK0084 (0x00100084)
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#define RSX_PFB_CFG0 (0x00100200)
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#define RSX_PFB_CFG0_SCRAMBLE 0x20000000
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#define RSX_PFB_CFG1 (0x00100204)
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#define RSX_PFB_FIFO_DATA (0x0010020C)
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#define RSX_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xFFF00000
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#define RSX_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
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#define RSX_PFB_FIFO_DATA_RAM_MODE_MASK 0x000FFFFF // DDR self refresh/refresh mode
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#define RSX_PFB_UNK0320 (0x00100320)
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#define RSX_PFB_UNK032C (0x0010032C) // Set by LV1 to 0xFFFF18FF
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#define RSX_PFB_UNK0330 (0x00100330) // Set by LV1 to 0xCCCC5044
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#define RSX_PFB_UNK0334 (0x00100334) // Set by LV1 to 0x33332022
|
||||
#define RSX_PFB_UNK0338 (0x00100338) // Set by LV1 to 0x0000000A
|
||||
#define RSX_PFB_CLOSE_PAGE2 (0x0010033C)
|
||||
#define RSX_PFB_UNK0340 (0x00100340) // Set by LV1 to 0x000001FB
|
||||
#define RSX_PFB_UNK0344 (0x00100344) // Set by LV1 to 0x00000000
|
||||
#define RSX_PFB_UNK0348 (0x00100348) // Set by LV1 to 0x00000000
|
||||
#define RSX_PFB_UNK0350 (0x00100350) // Set by LV1 to 0x0000440A
|
||||
#define RSX_PFB_UNK0354 (0x00100354) // Set by LV1 to 0x00000806
|
||||
#define RSX_PFB_TILE(i) (0x00100600 + 16*(i))
|
||||
#define RSX_PFB_TLIMIT(i) (0x00100604 + 16*(i))
|
||||
#define RSX_PFB_TSIZE(i) (0x00100608 + 16*(i))
|
||||
#define RSX_PFB_TSTATUS(i) (0x0010060C + 16*(i))
|
||||
|
||||
// PGRAPH
|
||||
#define RSX_PGRAPH_DEBUG_0 (0x00400080)
|
||||
#define RSX_PGRAPH_INTR (0x00400100)
|
||||
#define RSX_PGRAPH_UNK00A4 (0x004000A4)
|
||||
#define RSX_PGRAPH_NSOURCE (0x00400108)
|
||||
#define RSX_PGRAPH_NSOURCE_NOTIFICATION (1 << 0) // Notification pending
|
||||
#define RSX_PGRAPH_NSOURCE_DATA_ERROR (1 << 1) // Data error pending
|
||||
#define RSX_PGRAPH_NSOURCE_PROTECTION_ERROR (1 << 2) // Protection error
|
||||
#define RSX_PGRAPH_NSOURCE_RANGE_EXCEPTION (1 << 3) // Range exception pending
|
||||
#define RSX_PGRAPH_NSOURCE_LIMIT_COLOR (1 << 4) // Color limit erro pending
|
||||
#define RSX_PGRAPH_NSOURCE_LIMIT_ZETA (1 << 5) // Zeta limit erro pending
|
||||
#define RSX_PGRAPH_NSOURCE_ILLEGAL_MTHD (1 << 6) // Illegal method error pending
|
||||
#define RSX_PGRAPH_NSOURCE_DMA_R_PROTECTION (1 << 7) // DMA read protection error pending
|
||||
#define RSX_PGRAPH_NSOURCE_DMA_W_PROTECTION (1 << 8) // DMA write protection error pending
|
||||
#define RSX_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1 << 9) // Format exception error pending
|
||||
#define RSX_PGRAPH_NSOURCE_PATCH_EXCEPTION (1 << 10) // Patch exception error pending
|
||||
#define RSX_PGRAPH_NSOURCE_STATE_INVALID (1 << 11) // State invalid error pending
|
||||
#define RSX_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1 << 12) // Double notify error pending
|
||||
#define RSX_PGRAPH_NSOURCE_NOTIFY_IN_USE (1 << 13) // Notify in use pending
|
||||
#define RSX_PGRAPH_NSOURCE_METHOD_CNT (1 << 14) // Method count error pending
|
||||
#define RSX_PGRAPH_NSOURCE_BFR_NOTIFICATION (1 << 15) // Bfr notification erro pending
|
||||
#define RSX_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1 << 16) // DMA vertex protection error pending
|
||||
#define RSX_PGRAPH_NSOURCE_BIT17 (1 << 17) // Idx inline reuse error pending
|
||||
#define RSX_PGRAPH_NSOURCE_BIT18 (1 << 18) // Invalid operation error pending
|
||||
#define RSX_PGRAPH_NSOURCE_BIT22 (1 << 22) // Texture A protection error pending
|
||||
#define RSX_PGRAPH_NSOURCE_BIT23 (1 << 23) // Texture V protection error pending
|
||||
#define RSX_PGRAPH_NSOURCE_BIT24 (1 << 24) // DMA Z-Cull protection error pending
|
||||
#define RSX_PGRAPH_NSOURCE_BIT25 (1 << 25) // SIP error pending
|
||||
#define RSX_PGRAPH_CTX_CONTROL (0x00400144)
|
||||
#define RSX_PGRAPH_CTX_USER (0x00400148)
|
||||
#define RSX_PGRAPH_CTX_SWITCH(i) (0x0040014C + 4*(i))
|
||||
#define RSX_PGRAPH_CTXCTL_UNK0304 (0x00400304)
|
||||
#define RSX_PGRAPH_CTXCTL_UCODE_STAT 0x00400308
|
||||
#define RSX_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xFF000000
|
||||
#define RSX_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24
|
||||
#define RSX_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00FFFFFF
|
||||
#define RSX_PGRAPH_CTXCTL_UNK0310 (0x00400310)
|
||||
#define RSX_PGRAPH_CTXCTL_UCODE_INDEX (0x00400324)
|
||||
#define RSX_PGRAPH_CTXCTL_UCODE_DATA (0x00400328)
|
||||
#define RSX_PGRAPH_CTXCTL_CUR (0x0040032c)
|
||||
#define RSX_PGRAPH_CTXCTL_CUR_LOADED 0x01000000
|
||||
#define RSX_PGRAPH_CTXCTL_CUR_INSTANCE 0x000FFFFF
|
||||
#define RSX_PGRAPH_CTXCTL_NEXT (0x00400330)
|
||||
#define RSX_PGRAPH_CTXCTL_NEXT_INSTANCE 0x000FFFFF
|
||||
#define RSX_PGRAPH_DEBUG_2 (0x00400620)
|
||||
#define RSX_PGRAPH_UNK0634 (0x00400634)
|
||||
#define RSX_PGRAPH_TILE(i) (0x00400D00 + 16*(i))
|
||||
#define RSX_PGRAPH_DMA_A_XLATE_INST (0x00401040)
|
||||
#define RSX_PGRAPH_DMA_A_CONTROL (0x00401044)
|
||||
#define RSX_PGRAPH_DMA_A_LIMIT (0x00401048)
|
||||
#define RSX_PGRAPH_DMA_A_TLB_PTE (0x0040104C)
|
||||
#define RSX_PGRAPH_DMA_B_XLATE_INST (0x00401080)
|
||||
#define RSX_PGRAPH_DMA_B_CONTROL (0x00401084)
|
||||
#define RSX_PGRAPH_DMA_B_LIMIT (0x00401088)
|
||||
#define RSX_PGRAPH_DMA_B_TLB_PTE (0x0040108C)
|
||||
#define RSX_PGRAPH_UNK5000 (0x00405000)
|
||||
|
|
@ -13,7 +13,7 @@ using namespace gfx::hir;
|
|||
namespace gfx {
|
||||
namespace frontend {
|
||||
|
||||
Module* ShaderParser::parse(const char* data, size_t size) {
|
||||
Module* ShaderParser::parse(const char* data, Size size) {
|
||||
// NOTE: Assuming the input shader is designed for the only available frontend
|
||||
vulkan::VulkanShaderParser parser;
|
||||
return parser.parse(data, size);
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ namespace frontend {
|
|||
*/
|
||||
class ShaderParser {
|
||||
public:
|
||||
static hir::Module* parse(const char* data, size_t size);
|
||||
static hir::Module* parse(const char* data, Size size);
|
||||
};
|
||||
|
||||
} // namespace frontend
|
||||
|
|
|
|||
Loading…
Reference in a new issue