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hardware/liverpool: Explicitly state accessed registers

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This commit is contained in:
Alexandro Sanchez Bach 2021-11-04 13:42:22 +01:00
parent 475c1b5201
commit 25a08a4756
6 changed files with 181 additions and 155 deletions
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21
src/orbital/hardware/liverpool/amd_regs.h Normal file
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@ -0,0 +1,21 @@
/**
* AMD utility macros for registers.
*
* Copyright 2017-2021. Orbital project.
* Released under MIT license. Read LICENSE for more details.
*
* Authors:
* - Alexandro Sanchez Bach <alexandro@phi.nz>
*/
#pragma once
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
#define REG_SET_FIELD(orig_val, reg, field, field_val) \
(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
#define REG_GET_FIELD(value, reg, field) \
(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))

17
src/orbital/hardware/liverpool/bif/bif_regs.h Normal file
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@ -0,0 +1,17 @@
/**
* AMD Bus Interface (BIF) device.
*
* Copyright 2017-2021. Orbital project.
* Released under MIT license. Read LICENSE for more details.
*
* Authors:
* - Alexandro Sanchez Bach <alexandro@phi.nz>
*/
#pragma once
#include "bif/bif_4_1_d.h"
#include "bif/bif_4_1_sh_mask.h"
// Undocumented registers
#define mmCC_BIF_SECURE_CNTL 0x14E3

160
src/orbital/hardware/liverpool/liverpool_gc.cpp
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@ -9,11 +9,11 @@
*/
#include "liverpool_gc.h"
#include "amd_regs.h"
// Registers
#include "acp/acp.h"
#include "bif/bif_4_1_d.h"
#include "bif/bif_4_1_sh_mask.h"
#include "bif/bif_regs.h"
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
#include "gca/gfx_7_2_d.h"
@ -139,14 +139,14 @@ U64 LiverpoolGCDevice::mmio_read(U64 addr, U64 size) {
value = ih.mmio_read(index);
return value;
}
else if (SMU_MMIO.contains(index)) {
value = smu.mmio_read(index);
return value;
}
else if (SAM_MMIO.contains(index)) {
value = sam.mmio_read(index);
return value;
}
else if (SMU_MMIO.contains(index)) {
value = smu.mmio_read(index);
return value;
}
switch (index) {
// ACP
@ -160,18 +160,30 @@ U64 LiverpoolGCDevice::mmio_read(U64 addr, U64 size) {
value = 0xFFFFFFFF;
break;
// BIF
case mmBIF_FB_EN:
case mmBIOS_SCRATCH_7:
case mmGARLIC_FLUSH_CNTL:
case mmCC_BIF_SECURE_CNTL:
break;
// GCA
case mmGRBM_GFX_INDEX:
case mmRLC_MAX_PG_CU:
case mmRLC_PG_CNTL:
value = mmio[index];
// OSS
case mmSRBM_CNTL:
case mmHDP_ADDR_CONFIG:
case mmSEM_CHICKEN_BITS:
case mmHDP_HOST_PATH_CNTL:
break;
case mmCP_HQD_ACTIVE:
value = 0;
break;
case mmRLC_SERDES_CU_MASTER_BUSY:
value = 0;
// Unknown registers
case 0x13E:
case 0x1D0:
case 0x615:
case 0x618:
case 0x619:
case 0x61B:
case 0x3BD3:
case 0x3BD4:
case 0x3BD5:
break;
default:
@ -206,14 +218,14 @@ void LiverpoolGCDevice::mmio_write(U64 addr, U64 value, U64 size) {
ih.mmio_write(index, value);
return;
}
else if (SMU_MMIO.contains(index)) {
smu.mmio_write(index, value);
return;
}
else if (SAM_MMIO.contains(index)) {
sam.mmio_write(index, value);
return;
}
else if (SMU_MMIO.contains(index)) {
smu.mmio_write(index, value);
return;
}
// Indirect registers
switch (index) {
@ -230,87 +242,43 @@ void LiverpoolGCDevice::mmio_write(U64 addr, U64 value, U64 size) {
mmio[mmACP_SOFT_RESET] = (value << 16);
break;
// GCA
case mmGRBM_GFX_INDEX:
case mmRLC_PG_ALWAYS_ON_CU_MASK:
case mmRLC_MAX_PG_CU:
case mmRLC_PG_CNTL:
// OSS
case mmSRBM_CNTL:
break;
case mmSRBM_GFX_CNTL:
DPRINTF("mmSRBM_GFX_CNTL { me: %d, pipe: %d, queue: %d, vmid: %d }",
REG_GET_FIELD(value, SRBM_GFX_CNTL, MEID),
REG_GET_FIELD(value, SRBM_GFX_CNTL, PIPEID),
REG_GET_FIELD(value, SRBM_GFX_CNTL, QUEUEID),
REG_GET_FIELD(value, SRBM_GFX_CNTL, VMID));
break;
// GMC
case mmMC_SHARED_BLACKOUT_CNTL:
case mmMC_SEQ_RESERVE_0_S:
case mmMC_SEQ_RESERVE_1_S:
case mmMC_RPB_ARB_CNTL:
case mmMC_RPB_CID_QUEUE_WR:
case mmMC_RPB_WR_COMBINE_CNTL:
case mmMC_RPB_DBG1:
case mmMC_HUB_WDP_IH:
case mmMC_HUB_WDP_CPF:
case mmMC_HUB_RDREQ_CPC:
case mmMC_HUB_WDP_RLC:
case mmMC_HUB_RDREQ_UVD:
case mmMC_HUB_WRRET_MCDW:
case mmMC_HUB_RDREQ_DMIF:
case mmMC_HUB_RDREQ_CNTL:
case mmMC_HUB_RDREQ_MCDW:
case mmMC_HUB_RDREQ_MCDX:
case mmMC_HUB_RDREQ_MCDY:
case mmMC_HUB_RDREQ_MCDZ:
case mmMC_CITF_CREDITS_ARB_RD:
case mmMC_CITF_CREDITS_ARB_WR:
case mmMC_RD_GRP_EXT:
case mmMC_WR_GRP_EXT:
case mmMC_RD_GRP_LCL:
case mmMC_WR_GRP_LCL:
case mmMC_ARB_TM_CNTL_RD:
case mmMC_ARB_TM_CNTL_WR:
case mmMC_ARB_LAZY0_RD:
case mmMC_ARB_LAZY0_WR:
case mmMC_ARB_AGE_RD:
case mmMC_ARB_AGE_WR:
case mmMC_RD_GRP_GFX:
case mmMC_WR_GRP_GFX:
case mmMC_RD_GRP_SYS:
case mmMC_WR_GRP_SYS:
case mmMC_RD_GRP_OTH:
case mmMC_WR_GRP_OTH:
case mmMC_HUB_RDREQ_CPF:
case mmMC_HUB_WDP_ACPO:
case mmMC_ARB_WTM_CNTL_WR:
case mmMC_HUB_RDREQ_VMC:
case mmMC_ARB_WTM_CNTL_RD:
case mmMC_ARB_RET_CREDITS_WR:
case mmMC_ARB_LM_WR:
case mmMC_ARB_LM_RD:
case mmMC_ARB_RET_CREDITS_RD:
case mmMC_HUB_WDP_VCEU:
case mmMC_HUB_WDP_XDMAM:
case mmMC_HUB_WDP_XDMA:
case mmMC_HUB_RDREQ_XDMAM:
case mmMC_ARB_RET_CREDITS2:
case mmMC_SHARED_CHMAP:
case mmMC_ARB_SQM_CNTL:
case mmMC_BIST_MISMATCH_ADDR:
case mmMC_XPB_CLK_GAT:
case mmMC_HUB_MISC_SIP_CG:
case mmMC_HUB_MISC_HUB_CG:
case mmMC_HUB_MISC_VM_CG:
case mmMC_CITF_MISC_RD_CG:
case mmMC_CITF_MISC_WR_CG:
case mmMC_CITF_MISC_VM_CG:
case mmVM_L2_CG:
#ifdef NEEDSPORTING
break;
case mmCP_PFP_UCODE_DATA:
liverpool_gc_ucode_load(s, mmCP_PFP_UCODE_ADDR, value);
break;
case mmCP_CE_UCODE_DATA:
liverpool_gc_ucode_load(s, mmCP_CE_UCODE_ADDR, value);
break;
case mmCP_MEC_ME1_UCODE_DATA:
liverpool_gc_ucode_load(s, mmCP_MEC_ME1_UCODE_ADDR, value);
break;
case mmCP_MEC_ME2_UCODE_DATA:
liverpool_gc_ucode_load(s, mmCP_MEC_ME2_UCODE_ADDR, value);
break;
case mmRLC_GPM_UCODE_DATA:
liverpool_gc_ucode_load(s, mmRLC_GPM_UCODE_ADDR, value);
break;
/* oss */
case mmSDMA0_UCODE_DATA:
liverpool_gc_ucode_load(s, mmSDMA0_UCODE_ADDR, value);
break;
case mmSDMA1_UCODE_DATA:
liverpool_gc_ucode_load(s, mmSDMA1_UCODE_ADDR, value);
break;
#endif
// Simple registers
case mmSAM_IX_INDEX:
case mmSAM_GPR_SCRATCH_0:
case mmSAM_GPR_SCRATCH_1:
case mmSAM_GPR_SCRATCH_2:
case mmSAM_GPR_SCRATCH_3:
break;
default:
DPRINTF("index=0x%llX, size=0x%llX, value=0x%llX }", index, size, value);
assert_always("Unimplemented");

8
src/orbital/hardware/liverpool/sam/sam.cpp
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@ -11,6 +11,7 @@
*/
#include "sam.h"
#include "sam_regs.h"
#include <orbital/hardware/liverpool/gmc/gmc.h>
#include <orbital/hardware/liverpool/oss/ih.h>
#include <orbital/hardware/liverpool/smu/smu.h>
@ -40,6 +41,7 @@ SamDevice::SamDevice(GmcDevice& gmc, IhDevice& ih, SmuDevice& smu)
void SamDevice::reset() {
gpr.fill(0);
ih_cpu_am32_int_ctx = 0;
ih_cpu_am32_int_status = 0;
ih_am32_cpu_int_ctx = 0;
ix_data.fill(0);
@ -61,15 +63,15 @@ U32 SamDevice::mmio_read(U32 index) {
case ixSAM_IH_CPU_AM32_INT_CTX_LOW:
value = ih_cpu_am32_int_ctx_low;
break;
case ixSAM_IH_CPU_AM32_INT_STATUS:
value = ih_cpu_am32_int_status;
break;
case ixSAM_IH_AM32_CPU_INT_CTX_HIGH:
value = ih_am32_cpu_int_ctx_high;
break;
case ixSAM_IH_AM32_CPU_INT_CTX_LOW:
value = ih_am32_cpu_int_ctx_low;
break;
case ixSAM_IH_CPU_AM32_INT_STATUS:
value = ih_cpu_am32_int_status;
break;
default:
DPRINTF("mmSAM_IX_DATA_read { index: %X }", ix_index);
value = ix_data[ix_index];

57
src/orbital/hardware/liverpool/sam/sam.h
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@ -1,6 +1,6 @@
/**
* AMD Secure Asset Management Unit (SAMU) device.
*
*
* Based on research from: Alexey Kulaev (@flatz).
*
* Copyright 2017-2021. Orbital project.
@ -24,61 +24,6 @@ constexpr auto SAM_MMIO = OffsetRange(0x8800, 0x100);
constexpr auto SAM0_MMIO = OffsetRange(0x8800, 0x100);
constexpr auto SAM1_MMIO = OffsetRange(0x8900, 0x100);
// SAMU
#define mmSAM_IX_INDEX 0x8800
#define mmSAM_IX_DATA 0x8801
#define mmSAM_SAB_IX_INDEX 0x8802
#define mmSAM_SAB_IX_DATA 0x8803
#define mmSAM_IND_INDEX 0x8800
#define mmSAM_IND_DATA 0x8801
#define mmSAM_AM32_BOOT_BASE 0x8809
#define mmSAM_AM32_BOOT_OFFSET 0x880A
#define mmSAM_AM32_BOOT_LENGTH 0x880B
#define mmSAM_AM32_BOOT_CTRL 0x880C
#define mmSAM_AM32_BOOT_STATUS 0x880D
#define mmSAM_AM32_BOOT_HASH0 0x880E
#define mmSAM_AM32_BOOT_HASH1 0x880F
#define mmSAM_AM32_BOOT_HASH2 0x8810
#define mmSAM_AM32_BOOT_HASH3 0x8811
#define mmSAM_AM32_BOOT_HASH4 0x8812
#define mmSAM_AM32_BOOT_HASH5 0x8813
#define mmSAM_AM32_BOOT_HASH6 0x8814
#define mmSAM_AM32_BOOT_HASH7 0x8815
#define mmSAM_EMU_SRCID 0x8816
#define mmSAM_GPR_SCRATCH_4 0x8818
#define mmSAM_GPR_SCRATCH_5 0x8819
#define mmSAM_GPR_SCRATCH_6 0x881A
#define mmSAM_GPR_SCRATCH_7 0x881B
#define mmSAM_GPR_SCRATCH_0 0x881C
#define mmSAM_GPR_SCRATCH_1 0x881D
#define mmSAM_GPR_SCRATCH_2 0x881E
#define mmSAM_GPR_SCRATCH_3 0x881F
#define mmSAM_POWER_GATE 0x8834
#define mmSAM_BOOT_PWR_UP 0x8835
#define mmSAM_SMU_ALLOW_MEM_ACCESS 0x8836
#define mmSAM_PGFSM_CONFIG_REG 0x8837
#define mmSAM_PGFSM_WRITE_REG 0x8838
#define mmSAM_PGFSM_READ_REG 0x8839
#define mmSAM_PKI_FAIL_STATUS 0x883A
// SAMU IX
#define ixSAM_RST_HOST_SOFT_RESET 0x0001
#define ixSAM_CGC_HOST_CTRL 0x0003
#define ixSAM_IH_CPU_AM32_INT 0x0032
#define ixSAM_IH_CPU_AM32_INT_CTX_HIGH 0x0033
#define ixSAM_IH_CPU_AM32_INT_CTX_LOW 0x0034
#define ixSAM_IH_AM32_CPU_INT_CTX_HIGH 0x0035
#define ixSAM_IH_AM32_CPU_INT_CTX_LOW 0x0036
#define ixSAM_IH_AM32_CPU_INT_ACK 0x0037
#define ixSAM_UNK3E 0x003E
#define ixSAM_IH_CPU_AM32_INT_STATUS 0x004A
#define ixSAM_IH_AM32_CPU_INT_STATUS 0x004B
#define ixSAM_RST_HOST_SOFT_RST_RDY 0x0051
// SAMU SAB IX
#define ixSAM_SAB_INIT_TLB_CONFIG 0x0004
#define ixSAM_SAB_UNK29 0x0029
/* SAMU Commands */
struct samu_command_io_open_t {
char name[8];

73
src/orbital/hardware/liverpool/sam/sam_regs.h Normal file
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@ -0,0 +1,73 @@
/**
* AMD Secure Asset Management Unit (SAMU) device.
*
* Copyright 2017-2021. Orbital project.
* Released under MIT license. Read LICENSE for more details.
*
* Authors:
* - Alexandro Sanchez Bach <alexandro@phi.nz>
*/
#pragma once
// SAM block
#define mmSAM_IX_INDEX 0x8800
#define mmSAM_IX_DATA 0x8801
#define mmSAM_SAB_IX_INDEX 0x8802
#define mmSAM_SAB_IX_DATA 0x8803
#define mmSAM_IND_INDEX 0x8800
#define mmSAM_IND_DATA 0x8801
#define mmSAM_AM32_BOOT_BASE 0x8809
#define mmSAM_AM32_BOOT_OFFSET 0x880A
#define mmSAM_AM32_BOOT_LENGTH 0x880B
#define mmSAM_AM32_BOOT_CTRL 0x880C
#define mmSAM_AM32_BOOT_STATUS 0x880D
#define mmSAM_AM32_BOOT_HASH0 0x880E
#define mmSAM_AM32_BOOT_HASH1 0x880F
#define mmSAM_AM32_BOOT_HASH2 0x8810
#define mmSAM_AM32_BOOT_HASH3 0x8811
#define mmSAM_AM32_BOOT_HASH4 0x8812
#define mmSAM_AM32_BOOT_HASH5 0x8813
#define mmSAM_AM32_BOOT_HASH6 0x8814
#define mmSAM_AM32_BOOT_HASH7 0x8815
#define mmSAM_EMU_SRCID 0x8816
#define mmSAM_GPR_SCRATCH_4 0x8818
#define mmSAM_GPR_SCRATCH_5 0x8819
#define mmSAM_GPR_SCRATCH_6 0x881A
#define mmSAM_GPR_SCRATCH_7 0x881B
#define mmSAM_GPR_SCRATCH_0 0x881C
#define mmSAM_GPR_SCRATCH_1 0x881D
#define mmSAM_GPR_SCRATCH_2 0x881E
#define mmSAM_GPR_SCRATCH_3 0x881F
#define mmSAM_POWER_GATE 0x8834
#define mmSAM_BOOT_PWR_UP 0x8835
#define mmSAM_SMU_ALLOW_MEM_ACCESS 0x8836
#define mmSAM_PGFSM_CONFIG_REG 0x8837
#define mmSAM_PGFSM_WRITE_REG 0x8838
#define mmSAM_PGFSM_READ_REG 0x8839
#define mmSAM_PKI_FAIL_STATUS 0x883A
// SAMIND block
#define ixSAM_RST_HOST_SOFT_RESET 0x0001
#define ixSAM_CGC_HOST_CTRL 0x0003
#define ixSAM_IH_CPU_AM32_INT 0x0032
#define ixSAM_IH_CPU_AM32_INT_CTX_HIGH 0x0033
#define ixSAM_IH_CPU_AM32_INT_CTX_LOW 0x0034
#define ixSAM_IH_AM32_CPU_INT_CTX_HIGH 0x0035
#define ixSAM_IH_AM32_CPU_INT_CTX_LOW 0x0036
#define ixSAM_IH_AM32_CPU_INT_ACK 0x0037
#define ixSAM_SCRATCH_0 0x0038
#define ixSAM_SCRATCH_1 0x0039
#define ixSAM_SCRATCH_2 0x003A
#define ixSAM_SCRATCH_3 0x003B
#define ixSAM_SCRATCH_4 0x003C
#define ixSAM_SCRATCH_5 0x003D
#define ixSAM_SCRATCH_6 0x003E
#define ixSAM_SCRATCH_7 0x003F
#define ixSAM_IH_CPU_AM32_INT_STATUS 0x004A
#define ixSAM_IH_AM32_CPU_INT_STATUS 0x004B
#define ixSAM_RST_HOST_SOFT_RST_RDY 0x0051
// SABIND block
#define ixSAM_SAB_INIT_TLB_CONFIG 0x0004
#define ixSAM_SAB_EFUSE_STATUS_CNTL 0x0029