mirror of
https://github.com/hch12907/orbum.git
synced 2024-06-02 19:38:16 -04:00
Fixed code and formatting
- forgot to update the sticky flags - clang-format somehow messed up the formatting of OPM* instructions - RSQRT used wrong dividend - removed redundant clear_flags()
This commit is contained in:
hch12907
parent
ad9d719733
commit
289f10893d
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@ -38,8 +38,6 @@ void CVuInterpreter::ADD(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_2 = unit->vf[inst.ft()];
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -64,8 +62,6 @@ void CVuInterpreter::ADDi(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->i;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -90,8 +86,6 @@ void CVuInterpreter::ADDq(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->q;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -118,8 +112,6 @@ void CVuInterpreter::ADDbc(VuUnit_Base* unit, const VuInstruction inst, const in
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -168,8 +160,6 @@ void CVuInterpreter::ADDA(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_2 = unit->vf[inst.ft()];
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -194,8 +184,6 @@ void CVuInterpreter::ADDAi(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->i;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -220,8 +208,6 @@ void CVuInterpreter::ADDAq(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->q;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -248,8 +234,6 @@ void CVuInterpreter::ADDAbc(VuUnit_Base* unit, const VuInstruction inst, const i
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -299,8 +283,6 @@ void CVuInterpreter::SUB(VuUnit_Base* unit, const VuInstruction inst)
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auto& reg_source1 = unit->vf[inst.fs()];
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auto& reg_source2 = unit->vf[inst.ft()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -321,8 +303,6 @@ void CVuInterpreter::SUBi(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->i;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -347,8 +327,6 @@ void CVuInterpreter::SUBq(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->q;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -375,8 +353,6 @@ void CVuInterpreter::SUBbc(VuUnit_Base* unit, const VuInstruction inst, const in
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -425,8 +401,6 @@ void CVuInterpreter::SUBA(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_2 = unit->vf[inst.ft()];
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -451,8 +425,6 @@ void CVuInterpreter::SUBAi(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->i;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -477,8 +449,6 @@ void CVuInterpreter::SUBAq(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->q;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -505,8 +475,6 @@ void CVuInterpreter::SUBAbc(VuUnit_Base* unit, const VuInstruction inst, const i
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -555,8 +523,6 @@ void CVuInterpreter::MUL(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_2 = unit->vf[inst.ft()];
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -581,8 +547,6 @@ void CVuInterpreter::MULi(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->i;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -605,9 +569,7 @@ void CVuInterpreter::MULq(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedQwordRegister& reg_source_1 = unit->vf[inst.fs()];
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SizedWordRegister& reg_source_2 = unit->q;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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@ -635,8 +597,6 @@ void CVuInterpreter::MULbc(VuUnit_Base* unit, const VuInstruction inst, const in
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -685,8 +645,6 @@ void CVuInterpreter::MULA(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_2 = unit->vf[inst.ft()];
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -711,8 +669,6 @@ void CVuInterpreter::MULAi(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->i;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -737,8 +693,6 @@ void CVuInterpreter::MULAq(VuUnit_Base* unit, const VuInstruction inst)
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SizedWordRegister& reg_source_2 = unit->q;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -765,8 +719,6 @@ void CVuInterpreter::MULAbc(VuUnit_Base* unit, const VuInstruction inst, const i
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -816,8 +768,6 @@ void CVuInterpreter::MADD(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -844,8 +794,6 @@ void CVuInterpreter::MADDi(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -872,8 +820,6 @@ void CVuInterpreter::MADDq(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -902,8 +848,6 @@ void CVuInterpreter::MADDbc(VuUnit_Base* unit, const VuInstruction inst, const i
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -954,8 +898,6 @@ void CVuInterpreter::MADDA(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -982,8 +924,6 @@ void CVuInterpreter::MADDAi(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1010,8 +950,6 @@ void CVuInterpreter::MADDAq(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1040,8 +978,6 @@ void CVuInterpreter::MADDAbc(VuUnit_Base* unit, const VuInstruction inst, const
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1092,8 +1028,6 @@ void CVuInterpreter::MSUB(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1120,8 +1054,6 @@ void CVuInterpreter::MSUBi(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1148,8 +1080,6 @@ void CVuInterpreter::MSUBq(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1178,8 +1108,6 @@ void CVuInterpreter::MSUBbc(VuUnit_Base* unit, const VuInstruction inst, const i
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1230,8 +1158,6 @@ void CVuInterpreter::MSUBA(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1258,8 +1184,6 @@ void CVuInterpreter::MSUBAi(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1286,8 +1210,6 @@ void CVuInterpreter::MSUBAq(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& reg_source_3 = unit->acc;
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SizedQwordRegister& reg_dest = unit->acc;
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1316,8 +1238,6 @@ void CVuInterpreter::MSUBAbc(VuUnit_Base* unit, const VuInstruction inst, const
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// const ubyte bc = inst.bc();
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const ubyte bc = static_cast<ubyte>(idx);
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unit->status.clear_flags();
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FpuFlags flags;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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@ -1523,16 +1443,13 @@ void CVuInterpreter::OPMULA(VuUnit_Base* unit, const VuInstruction inst)
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FpuFlags flags;
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acc.write_float(VuVectorField::X, to_ps2_float(
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fs.read_float(VuVectorField::Y) * ft.read_float(VuVectorField::Z), flags));
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acc.write_float(VuVectorField::X, to_ps2_float(fs.read_float(VuVectorField::Y) * ft.read_float(VuVectorField::Z), flags));
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unit->mac.update_vector_field(VuVectorField::X, flags);
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acc.write_float(VuVectorField::Y, to_ps2_float(
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fs.read_float(VuVectorField::Z) * ft.read_float(VuVectorField::X), flags));
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acc.write_float(VuVectorField::Y, to_ps2_float(fs.read_float(VuVectorField::Z) * ft.read_float(VuVectorField::X), flags));
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unit->mac.update_vector_field(VuVectorField::Y, flags);
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acc.write_float(VuVectorField::Z, to_ps2_float(
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fs.read_float(VuVectorField::X) * ft.read_float(VuVectorField::Y), flags));
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acc.write_float(VuVectorField::Z, to_ps2_float(fs.read_float(VuVectorField::X) * ft.read_float(VuVectorField::Y), flags));
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unit->mac.update_vector_field(VuVectorField::Z, flags);
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}
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@ -1544,16 +1461,13 @@ void CVuInterpreter::OPMSUB(VuUnit_Base* unit, const VuInstruction inst)
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SizedQwordRegister& acc = unit->acc;
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FpuFlags flags;
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fd.write_float(VuVectorField::X, to_ps2_float(
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acc.read_float(VuVectorField::X) - fs.read_float(VuVectorField::Y) * ft.read_float(VuVectorField::Z), flags));
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fd.write_float(VuVectorField::X, to_ps2_float(acc.read_float(VuVectorField::X) - fs.read_float(VuVectorField::Y) * ft.read_float(VuVectorField::Z), flags));
|
||||
unit->mac.update_vector_field(VuVectorField::X, flags);
|
||||
|
||||
fd.write_float(VuVectorField::Y, to_ps2_float(
|
||||
acc.read_float(VuVectorField::Y) - fs.read_float(VuVectorField::Z) * ft.read_float(VuVectorField::X), flags));
|
||||
fd.write_float(VuVectorField::Y, to_ps2_float(acc.read_float(VuVectorField::Y) - fs.read_float(VuVectorField::Z) * ft.read_float(VuVectorField::X), flags));
|
||||
unit->mac.update_vector_field(VuVectorField::Y, flags);
|
||||
|
||||
fd.write_float(VuVectorField::Z, to_ps2_float(
|
||||
acc.read_float(VuVectorField::Z) - fs.read_float(VuVectorField::X) * ft.read_float(VuVectorField::Y), flags));
|
||||
fd.write_float(VuVectorField::Z, to_ps2_float(acc.read_float(VuVectorField::Z) - fs.read_float(VuVectorField::X) * ft.read_float(VuVectorField::Y), flags));
|
||||
unit->mac.update_vector_field(VuVectorField::Z, flags);
|
||||
}
|
||||
|
||||
|
|
@ -1565,17 +1479,19 @@ void CVuInterpreter::DIV(VuUnit_Base* unit, const VuInstruction inst)
|
|||
|
||||
FpuFlags flags;
|
||||
const float result = to_ps2_float(fs.read_float(inst.fsf()) / ft.read_float(inst.ftf()), flags);
|
||||
|
||||
unit->status.clear_flags();
|
||||
|
||||
// If ft[ftf] is 0, division by zero occurs...
|
||||
if (ft.read_float(inst.ftf()) == 0.0f)
|
||||
{
|
||||
if (fs.read_float(inst.ftf()) == 0.0f) {
|
||||
unit->status.insert_field(VuUnitRegister_Status::I, 1);
|
||||
// ...and if the dividend is 0, set the I flag, otherwise the D flag
|
||||
// See VU Users Manual pg 40
|
||||
if (fs.read_float(inst.fsf()) == 0.0f)
|
||||
{
|
||||
unit->status.set_i_flag_sticky(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
unit->status.insert_field(VuUnitRegister_Status::D, 1);
|
||||
unit->status.set_d_flag_sticky(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1588,14 +1504,14 @@ void CVuInterpreter::SQRT(VuUnit_Base* unit, const VuInstruction inst)
|
|||
SizedQwordRegister& ft = unit->vf[inst.ft()];
|
||||
|
||||
const float result = std::sqrt(std::abs(ft.read_float(inst.ftf())));
|
||||
|
||||
unit->status.clear_flags();
|
||||
|
||||
if ((ft.read_uword(inst.ftf()) >> 31 & 1) == 1) {
|
||||
unit->status.insert_field(VuUnitRegister_Status::I, 1);
|
||||
// If the float is negative, set the I flag
|
||||
if ((ft.read_uword(inst.ftf()) >> 31 & 1) == 1)
|
||||
{
|
||||
unit->status.set_i_flag_sticky(1);
|
||||
}
|
||||
|
||||
unit->status.insert_field(VuUnitRegister_Status::D, 0);
|
||||
unit->status.set_d_flag_sticky(0);
|
||||
|
||||
q.write_float(result);
|
||||
}
|
||||
|
|
@ -1604,19 +1520,20 @@ void CVuInterpreter::RSQRT(VuUnit_Base* unit, const VuInstruction inst)
|
|||
{
|
||||
SizedWordRegister& q = unit->q;
|
||||
SizedQwordRegister& ft = unit->vf[inst.ft()];
|
||||
SizedQwordRegister& fs = unit->vf[inst.fs()];
|
||||
|
||||
const float result = std::sqrt(std::abs(ft.read_float(inst.ftf())));
|
||||
|
||||
unit->status.clear_flags();
|
||||
|
||||
if ((ft.read_uword(inst.ftf()) >> 31 & 1) == 1) {
|
||||
unit->status.insert_field(VuUnitRegister_Status::I, 1);
|
||||
if ((ft.read_uword(inst.ftf()) >> 31 & 1) == 1)
|
||||
{
|
||||
unit->status.set_i_flag_sticky(1);
|
||||
}
|
||||
|
||||
if (ft.read_float(inst.ftf()) == 0.0f) {
|
||||
unit->status.insert_field(VuUnitRegister_Status::D, 1);
|
||||
if (ft.read_float(inst.ftf()) == 0.0f)
|
||||
{
|
||||
unit->status.set_d_flag_sticky(1);
|
||||
}
|
||||
|
||||
FpuFlags flag;
|
||||
q.write_float(to_ps2_float(1 / result, flag));
|
||||
q.write_float(to_ps2_float(fs.read_float(inst.fsf()) / result, flag));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue