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synced 2024-05-20 05:00:48 -04:00
Turn off logging for now - SIO2/SIO0 appears to work.
Currently the IOP is not sending any data to the SIO2 so I can't check anything further. Possibly waiting on the EE Core to do something?
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7e660980c9
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@ -120,8 +120,6 @@ void CSio0::handle_transfer()
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// Sequential command/response action.
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auto _stat_lock = stat.scope_lock();
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// Check there is data to send first, TX_RDY2 changes depending on this.
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if (!command_queue.has_read_available(1))
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{
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@ -133,11 +131,10 @@ void CSio0::handle_transfer()
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return;
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ubyte cmd = command_queue.read_ubyte();
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BOOST_LOG(Core::get_logger()) << str(boost::format("~~~~~ SIO0 received cmd: 0x%02X") % cmd);
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// TODO: properly implement, for now just send back 0x00 for all commands received.
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response_queue.write_ubyte(0);
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BOOST_LOG(Core::get_logger()) << "~~~~~ SIO0 sent response: 0x00 (not connected)";
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auto _stat_lock = stat.scope_lock();
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stat.insert_field(Sio0Register_Stat::RX_NONEMPTY, 1);
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}
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@ -85,9 +85,6 @@ void CSio2::handle_ctrl_check()
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// Reset direction bits - they are write only (see register description).
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ctrl.insert_field(Sio2Register_Ctrl::DIRECTION, 0);
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BOOST_LOG(Core::get_logger()) << str(boost::format("~~~~~~ SIO2 ctrl set: %s direction")
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% (ctrl.transfer_direction == Direction::TX ? "TX" : "RX"));
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ctrl.write_latch = false;
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}
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}
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@ -115,23 +112,11 @@ void CSio2::handle_port_trasnfer()
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if (!port.ctrl_3->port_transfer_started)
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{
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static bool warned = false;
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if (!port.ctrl_3->write_latch)
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{
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if (!warned)
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{
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BOOST_LOG(Core::get_logger()) << "~~~~~~ SIO2 TX/RX stalled: ctrl3 needs to be set by IOP first (write latch not set)";
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warned = true;
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}
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return;
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}
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warned = false;
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port.ctrl_3->port_transfer_started = true;
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port.ctrl_3->write_latch = false;
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BOOST_LOG(Core::get_logger()) << str(boost::format("~~~~~~ SIO2 TX port %d started") % ctrl.transfer_port);
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}
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switch (ctrl.transfer_direction)
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@ -155,13 +140,11 @@ void CSio2::handle_port_trasnfer()
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{
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if (ctrl.transfer_direction == Direction::RX)
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{
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BOOST_LOG(Core::get_logger()) << "~~~~~~ SIO2 RX finished: raising irq";
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auto& intc_stat = r.iop.intc.stat;
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auto _intc_lock = intc_stat.scope_lock();
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intc_stat.insert_field(IopIntcRegister_Stat::SIO2, 1);
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}
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BOOST_LOG(Core::get_logger()) << "~~~~~~ SIO2 TX or RX all ports finished";
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ctrl.transfer_started = false;
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}
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}
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@ -184,26 +167,17 @@ void CSio2::transfer_data_tx()
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if (ctrl.transfer_port_count != cmd_length)
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{
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if (!sio0_stat.extract_field(Sio0Register_Stat::TX_RDY1))
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{
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BOOST_LOG(Core::get_logger()) << "~~~~~~ SIO2 TX stalled: SIO0 stat.TX_RDY1 not set";
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return;
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}
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if (!data_in.has_read_available(1))
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{
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BOOST_LOG(Core::get_logger()) << "~~~~~~ SIO2 TX stalled: no FIFO data";
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return;
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}
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// If it's the first byte, perform some initialisation.
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if (ctrl.transfer_port_count == 0)
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{
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// Set the SIO0 pad port first when the SIO0 is ready.
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if (!sio0_stat.extract_field(Sio0Register_Stat::TX_RDY2))
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{
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BOOST_LOG(Core::get_logger()) << "~~~~~~ SIO2 TX stalled (init): SIO0 stat.TX_RDY2 not set";
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return;
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}
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uhword sio0_padport = port.ctrl_3->extract_field(Sio2PortRegister_Ctrl3::PADPORT);
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@ -219,7 +193,6 @@ void CSio2::transfer_data_tx()
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// Finished with this port, move on to next.
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if (ctrl.transfer_port_count == cmd_length)
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{
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BOOST_LOG(Core::get_logger()) << str(boost::format("~~~~~~ SIO2 TX port %d finished") % ctrl.transfer_port);
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ctrl.transfer_port += 1;
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ctrl.transfer_port_count = 0;
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}
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@ -241,16 +214,10 @@ void CSio2::transfer_data_rx()
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if (ctrl.transfer_port_count != response_length)
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{
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if (!data_out.has_write_available(1))
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{
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BOOST_LOG(Core::get_logger()) << "~~~~~~ SIO2 RX stalled: FIFO full";
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return;
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}
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if (!sio0_stat.extract_field(Sio0Register_Stat::RX_NONEMPTY))
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{
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BOOST_LOG(Core::get_logger()) << "~~~~~~ SIO2 RX stalled: SIO0 stat.RX_NONEMPTY not set";
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return;
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}
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ubyte data = sio0_data.read_ubyte();
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data_out.write_ubyte(data);
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@ -260,7 +227,6 @@ void CSio2::transfer_data_rx()
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// Finished with this port, move on to next.
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if (ctrl.transfer_port_count == response_length)
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{
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BOOST_LOG(Core::get_logger()) << str(boost::format("~~~~~~ SIO2 RX port %d finished") % ctrl.transfer_port);
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port.ctrl_3->port_transfer_started = false;
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ctrl.transfer_port += 1;
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ctrl.transfer_port_count = 0;
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