Implement M-bit handling

- only VU side, EE/COP2 side not implemented yet (another PR for that)
- this is a rough implementation, it doesnt even differentiate CPR and CCR
- also, a quick bugfix for WAITQ data hazard

liborbum/src/Controller/Ee/Vpu/Vu/CVu.cpp

@@ -41,4 +41,4 @@ int CVu::time_to_ticks(const double time_us)
     }
 
     return ticks;
-}
+}

liborbum/src/Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter.cpp

@@ -73,7 +73,12 @@ int CVuInterpreter::time_step(const int ticks_available)
         // (VU0 only)
         if (((raw_inst >> 61) & 1) && unit->core_id == 0)
         {
-            // TODO
+            VuUnit_Vu0& vu = r.ee.vpu.vu.unit_0;
+            if (vu.transferred_reg.has_value())
+            {
+                *vu.ccr[vu.transferred_reg_location] = vu.transferred_reg.value();
+                vu.transferred_reg = std::nullopt;
+            }
         }
 
         // If D (bit 60) and DE (in FBRST) is set, terminate the micro subroutine and interrupt
@@ -281,7 +286,7 @@ bool CVuInterpreter::check_data_hazard(VuUnit_Base* unit, const VuInstructionDec
     // If the instruction is WAITQ, return true if FDIV is running
     if ((decoder.get_lower_inst().value) & 0x7FF == 0x3BF)
     {
-        if (unit->efu.is_running()) return true;
+        if (unit->fdiv.is_running()) return true;
     }
 
     // Upper Instructions data hazard check

liborbum/src/Resources/Ee/Vpu/Vu/VuUnits.hpp

@@ -2,6 +2,7 @@
 
 #include <cereal/cereal.hpp>
 #include <cereal/types/polymorphic.hpp>
+#include <optional>
 
 #include "Common/Constants.hpp"
 #include "Common/Types/Bus/ByteBus.hpp"
@@ -135,6 +136,10 @@ public:
     /// Reference to the EE Core COP0 coprocessor, needed for the Status register.
     EeCoreCop0* cop0;
 
+    /// When M-bit is specified, this register is placed into its respective CCR.
+    int transferred_reg_location;
+    std::optional<SizedWordRegister> transferred_reg;
+
 public:
     template<class Archive>
     void serialize(Archive & archive)