mirror of
https://github.com/hch12907/orbum.git
synced 2024-06-01 19:08:05 -04:00
Implement VU pipelines
note: this commit can be reverted if pipeline emulation is found to be unneccessary - added MipsPipeline - implemented VU pipelines for the interpreter
This commit is contained in:
hch12907
parent
1d1212e57e
commit
56b5e45d84
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@ -22,6 +22,7 @@ set(COMMON_SRC_FILES
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"${CMAKE_SOURCE_DIR}/liborbum/src/Common/Types/Mips/MipsCoprocessor0.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Common/Types/Mips/MipsInstruction.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Common/Types/Mips/MipsInstructionInfo.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Common/Types/Mips/MipsPipeline.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Common/Types/Mips/MmuAccess.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Common/Types/Primitive.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Common/Types/Register/ByteRegister.hpp"
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@ -192,6 +193,8 @@ set(COMMON_SRC_FILES
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"${CMAKE_SOURCE_DIR}/liborbum/src/Resources/Ee/Vpu/Vu/VuBranchDelaySlot.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Resources/Ee/Vpu/Vu/VuInstruction.cpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Resources/Ee/Vpu/Vu/VuInstruction.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Resources/Ee/Vpu/Vu/VuPipelines.cpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Resources/Ee/Vpu/Vu/VuPipelines.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Resources/Ee/Vpu/Vu/VuRegisters.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Resources/Ee/Vpu/Vu/VuState.hpp"
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"${CMAKE_SOURCE_DIR}/liborbum/src/Resources/Ee/Vpu/Vu/VuUnitRegisters.cpp"
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@ -7,4 +7,5 @@ struct MipsInstructionInfo
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const char* const mnemonic; // A string representation of the instruction or subclass.
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const int impl_index; // Implementation index.
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const int cpi; // Cycles per instruction, used for timing.
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const int pipeline; // Pipeline used by the instruction, VU only.
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};
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48
liborbum/src/Common/Types/Mips/MipsPipeline.hpp
Normal file
48
liborbum/src/Common/Types/Mips/MipsPipeline.hpp
Normal file
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@ -0,0 +1,48 @@
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#pragma once
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#include "Common/Types/Primitive.hpp"
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/// The base class for representing the MIPS pipeline.
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struct MipsPipeline
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{
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MipsPipeline(uhword cycles = 0, uhword reg = 0) :
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finish_in(cycles),
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using_register(reg)
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{
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}
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public:
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/// Consumes specified cycle. The amount of cycles to be consumed is 1 by
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/// default.
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void consume_cycle(uhword cycles = 1)
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{
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finish_in -= cycles;
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}
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/// Flushes the pipeline, returning the amount of cycles it would had taken
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/// to finish the pipeline
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uhword flush_pipeline()
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{
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uhword cycles_consumed = finish_in;
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finish_in = 0;
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return cycles_consumed;
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}
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/// Checks whether the pipeline is still running.
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bool is_running() const
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{
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return finish_in > 0;
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}
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virtual bool is_using_register(uhword reg) const
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{
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return using_register == reg;
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}
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protected:
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// The cycles it takes to finish the pipeline execution
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uhword finish_in;
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// The register that is being used by the pipeline
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uhword using_register;
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};
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@ -12,13 +12,14 @@ CVuInterpreter::CVuInterpreter(Core* core) :
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int CVuInterpreter::time_step(const int ticks_available)
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{
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RResources& r = core->get_resources();
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// TODO: Not yet implemented.
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#if defined(BUILD_DEBUG)
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DEBUG_LOOP_COUNTER++;
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#endif
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RResources& r = core->get_resources();
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int cycles_consumed[2] = { 1, 1 };
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// The priority of register writing is: COP2 Transfer > Upper Inst > Lower Inst
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for (auto* unit : r.ee.vpu.vu.units)
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@ -31,23 +32,22 @@ int CVuInterpreter::time_step(const int ticks_available)
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// PC & Instructions stuff...
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const uword pc = unit->pc.read_uword() & 0x0FFF;
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const udword raw_inst = r.ee.bus.read_uword(BusContext::Vu, 0x11000000 + 0x8000 * unit->core_id + pc);
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const udword raw_inst = r.ee.bus.read_uword(BusContext::Vu, 0x11000000 | (0x8000 * unit->core_id + pc));
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const uword upper_raw_inst = (raw_inst >> 31) & 0xFFFFFFFF;
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const uword upper_raw_inst = (raw_inst >> 32) & 0xFFFFFFFF;
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const VuInstruction upper_inst = VuInstruction(upper_raw_inst);
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const MipsInstructionInfo upper_info = upper_inst.upper_lookup();
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const uword lower_raw_inst = raw_inst & 0xFFFFFFFF;
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const VuInstruction lower_inst = VuInstruction(lower_raw_inst);
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const MipsInstructionInfo lower_info = lower_inst.lower_lookup();
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// If I (bit 63) is set, execute UpperInst and LOI (using LowerInst as an immediate)
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if ((raw_inst >> 63) & 1)
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{
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(this->*VU_INSTRUCTION_TABLE[upper_inst.upper_lookup().impl_index])(unit, upper_inst);
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execute_upper_instruction(unit, upper_inst);
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this->LOI(unit, lower_inst);
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// Onto the next unit
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// Advance PC and onto the next unit
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unit->bdelay.advance_pc(unit->pc);
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continue;
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}
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@ -56,7 +56,7 @@ int CVuInterpreter::time_step(const int ticks_available)
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// Here we setup a delay slot for the next instruction
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if ((raw_inst >> 62) & 1)
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{
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if (unit->bdelay.is_branch_pending())
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if (unit->bdelay.is_branch_pending())
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{
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BOOST_LOG(Core::get_logger()) << "Found E-bit in branch delay slot";
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}
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@ -97,8 +97,8 @@ int CVuInterpreter::time_step(const int ticks_available)
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}
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}
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(this->*VU_INSTRUCTION_TABLE[lower_inst.lower_lookup().impl_index])(unit, lower_inst);
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(this->*VU_INSTRUCTION_TABLE[upper_inst.upper_lookup().impl_index])(unit, upper_inst);
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execute_lower_instruction(unit, lower_inst);
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execute_upper_instruction(unit, upper_inst);
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// Advance the PC
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unit->bdelay.advance_pc(unit->pc);
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@ -107,3 +107,140 @@ int CVuInterpreter::time_step(const int ticks_available)
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// TODO: Correct CPI
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return 1;
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}
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int CVuInterpreter::execute_lower_instruction(VuUnit_Base* unit, VuInstruction inst)
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{
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const MipsInstructionInfo info = inst.lower_lookup();
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switch (info.pipeline)
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{
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case VuPipeline::FDIV:
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{
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if (!unit->fdiv.is_running())
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{
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// FDIV is not responsible for the first 2 cycles (fetch instruction
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// and read registers)
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unit->fdiv = FdivPipeline(info.cpi - 2);
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// Temporarily save current Q in new_q, and swap it later
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// (needed because the instructions operate on unit->q)
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unit->fdiv.new_q = unit->q;
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(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
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std::swap(unit->q, unit->fdiv.new_q);
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break;
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}
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else
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{
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// Run the pipelines, and use the new registers if the pipeline is finished
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// Same for EFU etc
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unit->fdiv.consume_cycle(1);
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if (!unit->fdiv.is_running()) unit->q = unit->fdiv.new_q;
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}
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};
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case VuPipeline::EFU:
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{
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if (!unit->efu.is_running())
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{
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// The 3 cycles are for instruction fetching, and registers read/write.
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// EFU is responsible for the execution stages only.
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unit->efu = EfuPipeline(info.cpi - 3);
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// Temporarily save current P in new_p, and swap it later
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// (needed because the instructions operate on unit->p)
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unit->efu.new_p = unit->p;
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(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
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std::swap(unit->p, unit->efu.new_p);
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break;
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}
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else
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{
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unit->efu.consume_cycle(1);
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if (!unit->efu.is_running()) unit->p = unit->efu.new_p;
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}
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};
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case VuPipeline::IALU:
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{
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// See case EFU for the 3 cycles.
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// TODO: if an integer register is used during store/load data hazard is generated
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unit->ialu = IaluPipeline(info.cpi - 3);
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(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
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unit->ialu.consume_cycle(1);
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break;
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};
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case VuPipeline::Basic:
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{
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(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
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break;
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};
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default:
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throw std::runtime_error("VU: Found instruction of unsupported pipeline");
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}
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// Every step runs only 1 cycle except when the pipeline stalls
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return 1;
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}
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int CVuInterpreter::execute_upper_instruction(VuUnit_Base* unit, VuInstruction inst)
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{
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const MipsInstructionInfo info = inst.upper_lookup();
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for (FmacPipeline& fmac : unit->fmac)
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{
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// TODO: Data hazards occur when a register is being used by two
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// units/pipelines, but the current implementation tracks only
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bool is_type_3 = (inst.opcode() >> 2) == 0b1111;
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// If the VF register is being used, stall FMAC
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{
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// Upper Instruction field type 3 specifies only 2 registers, fs and ft,
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// while the others specifies 3 registers, fd, fs and ft.
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// (type 3 has the opcode 1111__)
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if (is_type_3)
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{
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if (fmac.is_using_register(inst.ft(), inst.dest()) ||
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fmac.is_using_register(inst.fs(), inst.dest()))
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{
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fmac.consume_cycle(1);
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continue;
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}
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}
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else
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{
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if (fmac.is_using_register(inst.fd(), inst.dest()) ||
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fmac.is_using_register(inst.fs(), inst.dest()) ||
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fmac.is_using_register(inst.ft(), inst.dest()))
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{
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fmac.consume_cycle(1);
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continue;
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}
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}
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}
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if (!fmac.is_running())
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{
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// FMAC has three execution stages, fixed for all the FMAC instructions
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if (is_type_3)
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fmac = FmacPipeline(3, inst.ft(), inst.dest());
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else
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fmac = FmacPipeline(3, inst.fd(), inst.dest());
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(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
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}
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else
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{
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fmac.consume_cycle(1);
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}
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}
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// Every step runs only 1 cycle except when the pipeline stalls
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return 1;
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}
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@ -381,4 +381,8 @@ public:
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&CVuInterpreter::XTOP,
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&CVuInterpreter::XITOP
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};
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private:
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int execute_upper_instruction(VuUnit_Base* unit, VuInstruction inst);
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int execute_lower_instruction(VuUnit_Base* unit, VuInstruction inst);
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};
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@ -1,4 +1,5 @@
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#include "Resources/Ee/Vpu/Vu/VuInstruction.hpp"
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#include "Resources/Ee/Vpu/Vu/VuPipelines.hpp"
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MipsInstructionInfo VU_INSTRUCTION_TABLE[Constants::EE::VPU::VU::NUMBER_VU_INSTRUCTIONS] =
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{
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@ -20,174 +21,180 @@ MipsInstructionInfo VU_INSTRUCTION_TABLE[Constants::EE::VPU::VU::NUMBER_VU_INSTR
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// Instructions prefixed with "I" utilizes the IALU unit. While calculation
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// is done in 1 cycle, there are 2 dummy stages (made to follow the FMACs),
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// which shows up in macro mode (normally the results are bypassed)
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// Branch instructions prefixed with "I" uses IALU too, but since the results
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// are bypassed and not used by CFC2, they are instead unified with other branch
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// instructions.
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// Some instructions (such as WAITP) are related to FDIV/EFU/IALU pipeline,
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// but they actually follow the basic pipeline...
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// Lower Instructions
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{"LQ", 109, 6},
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{"SQ", 112, 6},
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{"ILW", 115, 6},
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{"ISW", 116, 6},
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{"IADDIU", 100, 6},
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{"ISUBIU", 104, 6},
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{"FCEQ", 132, 6},
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{"FCSET", 134, 6},
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{"FCAND", 131, 6},
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{"FCOR", 133, 6},
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{"FSEQ", 125, 6},
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{"FSSET", 127, 6},
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{"FSAND", 124, 6},
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{"FSOR", 126, 6},
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{"FMEQ", 129, 6},
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{"FMAND", 128, 6},
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{"FMOR", 130, 6},
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{"FCGET", 135, 6},
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{"B", 142, 4},
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{"BAL", 143, 4},
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{"JR", 144, 4},
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{"JALR", 145, 4},
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{"IBEQ", 136, 4},
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{"IBNE", 141, 4},
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{"IBLTZ", 140, 4},
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{"IBGTZ", 138, 4},
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{"IBLEZ", 139, 4},
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{"IBGEZ", 137, 4},
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{"IADD", 98, 6},
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{"ISUB", 103, 6},
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{"IADDI", 99, 6},
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{"IAND", 101, 6},
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{"IOR", 102, 6},
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{"MOVE", 105, 6},
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{"LQI", 111, 6},
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{"DIV", 95, 9},
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{"MTIR", 107, 6},
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{"RNEXT", 121, 6},
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{"MFP", 146, 6},
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{"XTOP", 162, 6},
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{"XGKICK", 161, 6},
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{"ESADD", 148, 13},
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{"EATANxy", 152, 56},
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{"ESQRT", 156, 14},
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{"ESIN", 158, 31},
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{"MR32", 108, 6},
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{"SQI", 114, 6},
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{"SQRT", 96, 9},
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{"MFIR", 106, 6},
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{"RGET", 120, 6},
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{"XITOP", 163, 6},
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{"ERSADD", 149, 20},
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{"EATANxz", 153, 56},
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{"ERSQRT", 157, 20},
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{"EATAN", 159, 56},
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{"LQD", 110, 6},
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{"RSQRT", 97, 15},
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{"ILWR", 117, 6},
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{"RINIT", 119, 6},
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{"ELENG", 150, 20},
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{"ESUM", 154, 14},
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{"ERCPR", 155, 14},
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{"EEXP", 160, 46},
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{"SQD", 113, 6},
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{"WAITQ", 123, 6},
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{"ISWR", 118, 6},
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{"RXOR", 122, 6},
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{"ERLENG", 151, 26},
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{"WAITP", 147, 6},
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{"LQ", 109, 6, VuPipeline::Basic},
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{"SQ", 112, 6, VuPipeline::Basic},
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{"ILW", 115, 6, VuPipeline::Basic},
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{"ISW", 116, 6, VuPipeline::Basic},
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{"IADDIU", 100, 6, VuPipeline::IALU},
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{"ISUBIU", 104, 6, VuPipeline::IALU},
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{"FCEQ", 132, 6, VuPipeline::Basic},
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{"FCSET", 134, 6, VuPipeline::Basic},
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{"FCAND", 131, 6, VuPipeline::Basic},
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{"FCOR", 133, 6, VuPipeline::Basic},
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{"FSEQ", 125, 6, VuPipeline::Basic},
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{"FSSET", 127, 6, VuPipeline::Basic},
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{"FSAND", 124, 6, VuPipeline::Basic},
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{"FSOR", 126, 6, VuPipeline::Basic},
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{"FMEQ", 129, 6, VuPipeline::Basic},
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{"FMAND", 128, 6, VuPipeline::Basic},
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{"FMOR", 130, 6, VuPipeline::Basic},
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{"FCGET", 135, 6, VuPipeline::Basic},
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{"B", 142, 4, VuPipeline::Basic},
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{"BAL", 143, 4, VuPipeline::Basic},
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{"JR", 144, 4, VuPipeline::Basic},
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{"JALR", 145, 4, VuPipeline::Basic},
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{"IBEQ", 136, 4, VuPipeline::Basic},
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{"IBNE", 141, 4, VuPipeline::Basic},
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{"IBLTZ", 140, 4, VuPipeline::Basic},
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{"IBGTZ", 138, 4, VuPipeline::Basic},
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{"IBLEZ", 139, 4, VuPipeline::Basic},
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{"IBGEZ", 137, 4, VuPipeline::Basic},
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{"IADD", 98, 6, VuPipeline::IALU},
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{"ISUB", 103, 6, VuPipeline::IALU},
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{"IADDI", 99, 6, VuPipeline::IALU},
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{"IAND", 101, 6, VuPipeline::IALU},
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{"IOR", 102, 6, VuPipeline::IALU},
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{"MOVE", 105, 6, VuPipeline::Basic},
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{"LQI", 111, 6, VuPipeline::Basic},
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{"DIV", 95, 9, VuPipeline::FDIV},
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{"MTIR", 107, 6, VuPipeline::Basic},
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{"RNEXT", 121, 6, VuPipeline::Basic},
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{"MFP", 146, 6, VuPipeline::Basic},
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{"XTOP", 162, 6, VuPipeline::Basic},
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{"XGKICK", 161, 6, VuPipeline::Basic},
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{"ESADD", 148, 13, VuPipeline::EFU},
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{"EATANxy", 152, 56, VuPipeline::EFU},
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{"ESQRT", 156, 14, VuPipeline::EFU},
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{"ESIN", 158, 31, VuPipeline::EFU},
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{"MR32", 108, 6, VuPipeline::Basic},
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{"SQI", 114, 6, VuPipeline::Basic},
|
||||
{"SQRT", 96, 9, VuPipeline::FDIV},
|
||||
{"MFIR", 106, 6, VuPipeline::Basic},
|
||||
{"RGET", 120, 6, VuPipeline::Basic},
|
||||
{"XITOP", 163, 6, VuPipeline::Basic},
|
||||
{"ERSADD", 149, 20, VuPipeline::EFU},
|
||||
{"EATANxz", 153, 56, VuPipeline::EFU},
|
||||
{"ERSQRT", 157, 20, VuPipeline::EFU},
|
||||
{"EATAN", 159, 56, VuPipeline::EFU},
|
||||
{"LQD", 110, 6, VuPipeline::Basic},
|
||||
{"RSQRT", 97, 15, VuPipeline::FDIV},
|
||||
{"ILWR", 117, 6, VuPipeline::Basic},
|
||||
{"RINIT", 119, 6, VuPipeline::Basic},
|
||||
{"ELENG", 150, 20, VuPipeline::EFU},
|
||||
{"ESUM", 154, 14, VuPipeline::EFU},
|
||||
{"ERCPR", 155, 14, VuPipeline::EFU},
|
||||
{"EEXP", 160, 46, VuPipeline::EFU},
|
||||
{"SQD", 113, 6, VuPipeline::Basic},
|
||||
{"WAITQ", 123, 6, VuPipeline::FDIV},
|
||||
{"ISWR", 118, 6, VuPipeline::Basic},
|
||||
{"RXOR", 122, 6, VuPipeline::Basic},
|
||||
{"ERLENG", 151, 26, VuPipeline::EFU},
|
||||
{"WAITP", 147, 6, VuPipeline::EFU},
|
||||
|
||||
// Upper Instructions
|
||||
{"ADDbc_0", 4, 6},
|
||||
{"ADDbc_1", 5, 6},
|
||||
{"ADDbc_2", 6, 6},
|
||||
{"ADDbc_3", 7, 6},
|
||||
{"SUBbc_0", 18, 6},
|
||||
{"SUBbc_1", 19, 6},
|
||||
{"SUBbc_2", 20, 6},
|
||||
{"SUBbc_3", 21, 6},
|
||||
{"MADDbc_0", 46, 6},
|
||||
{"MADDbc_1", 47, 6},
|
||||
{"MADDbc_2", 48, 6},
|
||||
{"MADDbc_3", 49, 6},
|
||||
{"MSUBbc_0", 60, 6},
|
||||
{"MSUBbc_1", 61, 6},
|
||||
{"MSUBbc_2", 62, 6},
|
||||
{"MSUBbc_3", 63, 6},
|
||||
{"MAXbc_0", 73, 6},
|
||||
{"MAXbc_1", 74, 6},
|
||||
{"MAXbc_2", 75, 6},
|
||||
{"MAXbc_3", 76, 6},
|
||||
{"MINIbc_0", 79, 6},
|
||||
{"MINIbc_1", 80, 6},
|
||||
{"MINIbc_2", 81, 6},
|
||||
{"MINIbc_3", 82, 6},
|
||||
{"MULbc_0", 32, 6},
|
||||
{"MULbc_1", 33, 6},
|
||||
{"MULbc_2", 34, 6},
|
||||
{"MULbc_3", 35, 6},
|
||||
{"MULq", 31, 6},
|
||||
{"MAXi", 72, 6},
|
||||
{"MULi", 30, 6},
|
||||
{"MINIi", 78, 6},
|
||||
{"ADDq", 3, 6},
|
||||
{"MADDq", 45, 6},
|
||||
{"ADDi", 2, 6},
|
||||
{"MADDi", 44, 6},
|
||||
{"SUBq", 17, 6},
|
||||
{"MSUBq", 59, 6},
|
||||
{"SUBi", 16, 6},
|
||||
{"MSUBi", 58, 6},
|
||||
{"ADD", 1, 6},
|
||||
{"MADD", 43, 6},
|
||||
{"MUL", 29, 6},
|
||||
{"MAX", 71, 6},
|
||||
{"SUB", 15, 6},
|
||||
{"MSUB", 57, 6},
|
||||
{"OPMSUB", 84, 6},
|
||||
{"MINI", 77, 6},
|
||||
{"ADDAbc_0", 11, 6},
|
||||
{"SUBAbc_0", 25, 6},
|
||||
{"MADDAbc_0", 53, 6},
|
||||
{"MSUBAbc_0", 67, 6},
|
||||
{"ITOF0", 90, 6},
|
||||
{"FTOI0", 86, 6},
|
||||
{"MULAbc_0", 39, 6},
|
||||
{"MULAq", 38, 6},
|
||||
{"ADDAq", 10, 6},
|
||||
{"SUBAq", 24, 6},
|
||||
{"ADDA", 8, 6},
|
||||
{"SUBA", 22, 6},
|
||||
{"ADDAbc_1", 12, 6},
|
||||
{"SUBAbc_1", 26, 6},
|
||||
{"MADDAbc_1", 54, 6},
|
||||
{"MSUBAbc_1", 68, 6},
|
||||
{"ITOF4", 91, 6},
|
||||
{"FTOI4", 87, 6},
|
||||
{"MULAbc_1", 40, 6},
|
||||
{"ABS", 0, 6},
|
||||
{"MADDAq", 52, 6},
|
||||
{"MSUBAq", 66, 6},
|
||||
{"MADDA", 50, 6},
|
||||
{"MSUBA", 64, 6},
|
||||
{"ADDAbc_2", 13, 6},
|
||||
{"SUBAbc_2", 27, 6},
|
||||
{"MADDAbc_2", 55, 6},
|
||||
{"MSUBAbc_2", 69, 6},
|
||||
{"ITOF12", 92, 6},
|
||||
{"FTOI12", 88, 6},
|
||||
{"MULAbc_2", 41, 6},
|
||||
{"MULAi", 37, 6},
|
||||
{"ADDAi", 9, 6},
|
||||
{"SUBAi", 23, 6},
|
||||
{"MULA", 36, 6},
|
||||
{"OPMULA", 83, 6},
|
||||
{"ADDAbc_3", 14, 6},
|
||||
{"SUBAbc_3", 28, 6},
|
||||
{"MADDAbc_3", 56, 6},
|
||||
{"MSUBAbc_3", 70, 6},
|
||||
{"ITOF15", 93, 6},
|
||||
{"FTOI15", 89, 6},
|
||||
{"MULAbc_3", 42, 6},
|
||||
{"CLIP", 94, 6},
|
||||
{"MADDAi", 51, 6},
|
||||
{"MSUBAi", 65, 6},
|
||||
{"NOP", 85, 6}};
|
||||
{"ADDbc_0", 4, 6, VuPipeline::FMAC},
|
||||
{"ADDbc_1", 5, 6, VuPipeline::FMAC},
|
||||
{"ADDbc_2", 6, 6, VuPipeline::FMAC},
|
||||
{"ADDbc_3", 7, 6, VuPipeline::FMAC},
|
||||
{"SUBbc_0", 18, 6, VuPipeline::FMAC},
|
||||
{"SUBbc_1", 19, 6, VuPipeline::FMAC},
|
||||
{"SUBbc_2", 20, 6, VuPipeline::FMAC},
|
||||
{"SUBbc_3", 21, 6, VuPipeline::FMAC},
|
||||
{"MADDbc_0", 46, 6, VuPipeline::FMAC},
|
||||
{"MADDbc_1", 47, 6, VuPipeline::FMAC},
|
||||
{"MADDbc_2", 48, 6, VuPipeline::FMAC},
|
||||
{"MADDbc_3", 49, 6, VuPipeline::FMAC},
|
||||
{"MSUBbc_0", 60, 6, VuPipeline::FMAC},
|
||||
{"MSUBbc_1", 61, 6, VuPipeline::FMAC},
|
||||
{"MSUBbc_2", 62, 6, VuPipeline::FMAC},
|
||||
{"MSUBbc_3", 63, 6, VuPipeline::FMAC},
|
||||
{"MAXbc_0", 73, 6, VuPipeline::FMAC},
|
||||
{"MAXbc_1", 74, 6, VuPipeline::FMAC},
|
||||
{"MAXbc_2", 75, 6, VuPipeline::FMAC},
|
||||
{"MAXbc_3", 76, 6, VuPipeline::FMAC},
|
||||
{"MINIbc_0", 79, 6, VuPipeline::FMAC},
|
||||
{"MINIbc_1", 80, 6, VuPipeline::FMAC},
|
||||
{"MINIbc_2", 81, 6, VuPipeline::FMAC},
|
||||
{"MINIbc_3", 82, 6, VuPipeline::FMAC},
|
||||
{"MULbc_0", 32, 6, VuPipeline::FMAC},
|
||||
{"MULbc_1", 33, 6, VuPipeline::FMAC},
|
||||
{"MULbc_2", 34, 6, VuPipeline::FMAC},
|
||||
{"MULbc_3", 35, 6, VuPipeline::FMAC},
|
||||
{"MULq", 31, 6, VuPipeline::FMAC},
|
||||
{"MAXi", 72, 6, VuPipeline::FMAC},
|
||||
{"MULi", 30, 6, VuPipeline::FMAC},
|
||||
{"MINIi", 78, 6, VuPipeline::FMAC},
|
||||
{"ADDq", 3, 6, VuPipeline::FMAC},
|
||||
{"MADDq", 45, 6, VuPipeline::FMAC},
|
||||
{"ADDi", 2, 6, VuPipeline::FMAC},
|
||||
{"MADDi", 44, 6, VuPipeline::FMAC},
|
||||
{"SUBq", 17, 6, VuPipeline::FMAC},
|
||||
{"MSUBq", 59, 6, VuPipeline::FMAC},
|
||||
{"SUBi", 16, 6, VuPipeline::FMAC},
|
||||
{"MSUBi", 58, 6, VuPipeline::FMAC},
|
||||
{"ADD", 1, 6, VuPipeline::FMAC},
|
||||
{"MADD", 43, 6, VuPipeline::FMAC},
|
||||
{"MUL", 29, 6, VuPipeline::FMAC},
|
||||
{"MAX", 71, 6, VuPipeline::FMAC},
|
||||
{"SUB", 15, 6, VuPipeline::FMAC},
|
||||
{"MSUB", 57, 6, VuPipeline::FMAC},
|
||||
{"OPMSUB", 84, 6, VuPipeline::FMAC},
|
||||
{"MINI", 77, 6, VuPipeline::FMAC},
|
||||
{"ADDAbc_0", 11, 6, VuPipeline::FMAC},
|
||||
{"SUBAbc_0", 25, 6, VuPipeline::FMAC},
|
||||
{"MADDAbc_0", 53, 6, VuPipeline::FMAC},
|
||||
{"MSUBAbc_0", 67, 6, VuPipeline::FMAC},
|
||||
{"ITOF0", 90, 6, VuPipeline::FMAC},
|
||||
{"FTOI0", 86, 6, VuPipeline::FMAC},
|
||||
{"MULAbc_0", 39, 6, VuPipeline::FMAC},
|
||||
{"MULAq", 38, 6, VuPipeline::FMAC},
|
||||
{"ADDAq", 10, 6, VuPipeline::FMAC},
|
||||
{"SUBAq", 24, 6, VuPipeline::FMAC},
|
||||
{"ADDA", 8, 6, VuPipeline::FMAC},
|
||||
{"SUBA", 22, 6, VuPipeline::FMAC},
|
||||
{"ADDAbc_1", 12, 6, VuPipeline::FMAC},
|
||||
{"SUBAbc_1", 26, 6, VuPipeline::FMAC},
|
||||
{"MADDAbc_1", 54, 6, VuPipeline::FMAC},
|
||||
{"MSUBAbc_1", 68, 6, VuPipeline::FMAC},
|
||||
{"ITOF4", 91, 6, VuPipeline::FMAC},
|
||||
{"FTOI4", 87, 6, VuPipeline::FMAC},
|
||||
{"MULAbc_1", 40, 6, VuPipeline::FMAC},
|
||||
{"ABS", 0, 6, VuPipeline::FMAC},
|
||||
{"MADDAq", 52, 6, VuPipeline::FMAC},
|
||||
{"MSUBAq", 66, 6, VuPipeline::FMAC},
|
||||
{"MADDA", 50, 6, VuPipeline::FMAC},
|
||||
{"MSUBA", 64, 6, VuPipeline::FMAC},
|
||||
{"ADDAbc_2", 13, 6, VuPipeline::FMAC},
|
||||
{"SUBAbc_2", 27, 6, VuPipeline::FMAC},
|
||||
{"MADDAbc_2", 55, 6, VuPipeline::FMAC},
|
||||
{"MSUBAbc_2", 69, 6, VuPipeline::FMAC},
|
||||
{"ITOF12", 92, 6, VuPipeline::FMAC},
|
||||
{"FTOI12", 88, 6, VuPipeline::FMAC},
|
||||
{"MULAbc_2", 41, 6, VuPipeline::FMAC},
|
||||
{"MULAi", 37, 6, VuPipeline::FMAC},
|
||||
{"ADDAi", 9, 6, VuPipeline::FMAC},
|
||||
{"SUBAi", 23, 6, VuPipeline::FMAC},
|
||||
{"MULA", 36, 6, VuPipeline::FMAC},
|
||||
{"OPMULA", 83, 6, VuPipeline::FMAC},
|
||||
{"ADDAbc_3", 14, 6, VuPipeline::FMAC},
|
||||
{"SUBAbc_3", 28, 6, VuPipeline::FMAC},
|
||||
{"MADDAbc_3", 56, 6, VuPipeline::FMAC},
|
||||
{"MSUBAbc_3", 70, 6, VuPipeline::FMAC},
|
||||
{"ITOF15", 93, 6, VuPipeline::FMAC},
|
||||
{"FTOI15", 89, 6, VuPipeline::FMAC},
|
||||
{"MULAbc_3", 42, 6, VuPipeline::FMAC},
|
||||
{"CLIP", 94, 6, VuPipeline::FMAC},
|
||||
{"MADDAi", 51, 6, VuPipeline::FMAC},
|
||||
{"MSUBAi", 65, 6, VuPipeline::FMAC},
|
||||
{"NOP", 85, 6, VuPipeline::FMAC}};
|
||||
|
||||
MipsInstructionInfo VuInstruction::lower_lookup() const
|
||||
{
|
||||
|
|
|
|||
1
liborbum/src/Resources/Ee/Vpu/Vu/VuPipelines.cpp
Normal file
1
liborbum/src/Resources/Ee/Vpu/Vu/VuPipelines.cpp
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include "Resources/Ee/Vpu/Vu/VuPipelines.hpp"
|
||||
82
liborbum/src/Resources/Ee/Vpu/Vu/VuPipelines.hpp
Normal file
82
liborbum/src/Resources/Ee/Vpu/Vu/VuPipelines.hpp
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
#pragma once
|
||||
|
||||
#include "Common/Types/Mips/MipsPipeline.hpp"
|
||||
#include "Common/Types/Register/SizedWordRegister.hpp"
|
||||
|
||||
struct VuPipeline
|
||||
{
|
||||
enum {
|
||||
FMAC = 0,
|
||||
FDIV = 1,
|
||||
EFU = 2,
|
||||
IALU = 3,
|
||||
|
||||
Basic = 4, // LSU, BRU, RANDU etc follow this. Similar to FMAC, but doesn't use FMAC units
|
||||
};
|
||||
};
|
||||
|
||||
/// The FMAC pipeline.
|
||||
///
|
||||
/// There are in total 4 FMAC units in a VU (each corresponding to a field).
|
||||
/// Resource hazard is not generated for the FMAC pipeline, only data hazards.
|
||||
/// When the same field of the same register is accessed by 2 different FMAC units
|
||||
/// stalling occurs.
|
||||
struct FmacPipeline : public MipsPipeline
|
||||
{
|
||||
FmacPipeline(uhword cycles = 0, uhword reg = 0, ubyte field = 0) :
|
||||
MipsPipeline(cycles, (reg << 4) | field)
|
||||
{
|
||||
}
|
||||
|
||||
bool is_using_register(uhword reg) const override
|
||||
{
|
||||
return is_using_register(reg >> 4, reg & 0b1111);
|
||||
}
|
||||
|
||||
bool is_using_register(ubyte reg, size_t field) const
|
||||
{
|
||||
const uhword using_reg = using_register >> 4;
|
||||
const uhword reg_field = using_register & 0b1111;
|
||||
|
||||
// True if the pipeline is running, is using the same register, and is using the same fields
|
||||
// Also true if it is VF00 that is being written into (it is hardwired to 0)
|
||||
return (reg == 0) || (is_running() && (using_reg == reg) && ((reg_field ^ field) != 0b1111));
|
||||
}
|
||||
};
|
||||
|
||||
/// The FDIV pipeline.
|
||||
///
|
||||
/// When a DIV instruction is executed while the pipeline is still running, a
|
||||
/// resource hazard is generated and the instruction is stalled until the write-back
|
||||
/// stage. Furthermore, when a Upper Instruction uses the Q register while the
|
||||
/// pipeline is still running, FMAC will not stall and will use the original
|
||||
/// Q register instead.
|
||||
struct FdivPipeline : public MipsPipeline
|
||||
{
|
||||
using MipsPipeline::MipsPipeline;
|
||||
|
||||
SizedWordRegister new_q;
|
||||
};
|
||||
|
||||
/// The EFU pipeline.
|
||||
///
|
||||
/// The EFU pipeline is pretty similar to the FDIV pipeline, except that the
|
||||
/// instruction is stalled until the last stage of the execution, not write-back.
|
||||
/// (NOTE: the next instruction starts during the write-back stage!)
|
||||
struct EfuPipeline : public MipsPipeline
|
||||
{
|
||||
using MipsPipeline::MipsPipeline;
|
||||
|
||||
SizedWordRegister new_p;
|
||||
};
|
||||
|
||||
/// The IALU pipeline.
|
||||
///
|
||||
/// IALU takes only one cycle to execute, but there are 2 dummy stages needed
|
||||
/// to go through before the result is written back to the registers, though
|
||||
/// the result can bypass directly to other pipelines and stalls do not occur
|
||||
/// except when it is transferred with CFC2.
|
||||
struct IaluPipeline : public MipsPipeline
|
||||
{
|
||||
using MipsPipeline::MipsPipeline;
|
||||
};
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
#include "Common/Types/Register/SizedHwordRegister.hpp"
|
||||
#include "Common/Types/Register/SizedQwordRegister.hpp"
|
||||
#include "Resources/Ee/Vpu/Vu/VuBranchDelaySlot.hpp"
|
||||
#include "Resources/Ee/Vpu/Vu/VuPipelines.hpp"
|
||||
#include "Resources/Ee/Vpu/Vu/VuState.hpp"
|
||||
#include "Resources/Ee/Vpu/Vu/VuUnitRegisters.hpp"
|
||||
|
||||
|
|
@ -82,6 +83,12 @@ public:
|
|||
/// VU operation state. The VU has 3 operation states: Ready, Run, Stop.
|
||||
VuOperationState operation_state;
|
||||
|
||||
/// VU pipelines.
|
||||
FmacPipeline fmac[4];
|
||||
FdivPipeline fdiv;
|
||||
EfuPipeline efu;
|
||||
IaluPipeline ialu;
|
||||
|
||||
public:
|
||||
template<class Archive>
|
||||
void serialize(Archive & archive)
|
||||
|
|
|
|||
Loading…
Reference in a new issue