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Fix up all errors...

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This commit is contained in:
Marco Satti 2018-08-08 22:51:39 +08:00
parent f9c6862156
commit 99f502c4cc
31 changed files with 167 additions and 71 deletions
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17
liborbum/src/Common/Types/Register/SizedByteRegister.hpp
View file

@ -31,14 +31,6 @@ public:
b = value;
}
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(b)
);
}
private:
/// Primitive (sized) storage for register.
union {
@ -51,4 +43,13 @@ private:
/// Read-only flag.
/// Writes are silently discarded if turned on.
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(b)
);
}
};

17
liborbum/src/Common/Types/Register/SizedDwordRegister.hpp
View file

@ -97,14 +97,6 @@ public:
d = value;
}
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(d)
);
}
private:
/// Primitive (sized) storage for register.
union {
@ -120,4 +112,13 @@ private:
/// Read-only flag.
/// Writes are silently discarded if turned on.
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(d)
);
}
};

17
liborbum/src/Common/Types/Register/SizedHwordRegister.hpp
View file

@ -55,14 +55,6 @@ public:
h = value;
}
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(h)
);
}
private:
/// Primitive (sized) storage for register.
union {
@ -76,4 +68,13 @@ private:
/// Read-only flag.
/// Writes are silently discarded if turned on.
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(h)
);
}
};

17
liborbum/src/Common/Types/Register/SizedQwordRegister.hpp
View file

@ -118,14 +118,6 @@ public:
q = value;
}
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(q)
);
}
private:
/// Primitive (sized) storage for register.
union {
@ -142,4 +134,13 @@ private:
/// Read-only flag.
/// Writes are silently discarded if turned on.
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(q)
);
}
};

17
liborbum/src/Common/Types/Register/SizedWordRegister.hpp
View file

@ -76,14 +76,6 @@ public:
w = value;
}
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(w)
);
}
private:
/// Primitive (sized) storage for register.
union {
@ -98,4 +90,13 @@ private:
/// Read-only flag.
/// Writes are silently discarded if turned on.
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
CEREAL_NVP(w)
);
}
};

5
liborbum/src/Controller/Ee/Timers/CEeTimers.cpp
View file

@ -58,12 +58,13 @@ void CEeTimers::tick_timer(const ControllerEvent::Type ce_type)
for (auto& unit : r.ee.timers.units)
{
auto _lock = unit.mode->scope_lock();
auto[prescale, event_type] = unit.mode->get_properties();
// Check if we need to perform reset proceedures.
if (unit.mode->write_latch)
{
// Reset the count register.
uword prescale = unit.mode->calculate_prescale_and_set_event();
unit.count->reset_prescale(prescale);
unit.mode->write_latch = false;
@ -71,7 +72,7 @@ void CEeTimers::tick_timer(const ControllerEvent::Type ce_type)
// Count only if enabled.
bool unit_enabled = unit.mode->extract_field(EeTimersUnitRegister_Mode::CUE);
bool is_same_clk_source = ce_type == unit.mode->event_type;
bool is_same_clk_source = ce_type == event_type;
if (!unit_enabled || !is_same_clk_source)
continue;

11
liborbum/src/Controller/Iop/Timers/CIopTimers.cpp
View file

@ -58,23 +58,18 @@ void CIopTimers::tick_timer(const ControllerEvent::Type ce_type)
{
auto _lock = unit->mode.scope_lock();
auto[prescale, event_type] = unit->mode.get_properties(unit->unit_id);
// Check if we need to perform reset proceedures.
if (unit->mode.write_latch)
{
// Work out if the timer is used meaningfully (enabled).
bool irq_on_of = unit->mode.extract_field(IopTimersUnitRegister_Mode::IRQ_ON_OF) > 0;
bool irq_on_target = unit->mode.extract_field(IopTimersUnitRegister_Mode::IRQ_ON_TARGET) > 0;
unit->mode.is_enabled = irq_on_of || irq_on_target;
// Reset the count register.
uword prescale = unit->mode.calculate_prescale_and_set_event(unit->unit_id);
unit->count.reset_prescale(prescale);
unit->mode.write_latch = false;
}
// Count only if the timer is "enabled", and mode is equal to the event source.
if (!unit->mode.is_enabled || ce_type != unit->mode.event_type)
if (!unit->mode.is_enabled() || ce_type != event_type)
continue;
// Perform a gated tick if on, else increment normally.

2
liborbum/src/Resources/Cdvd/CdvdRegisters.hpp
View file

@ -1,5 +1,7 @@
#pragma once
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Bitfield.hpp"
#include "Common/Types/FifoQueue/DmaFifoQueue.hpp"
#include "Common/Types/Register/ByteRegister.hpp"

4
liborbum/src/Resources/Ee/Core/EeCoreCop0Registers.hpp
View file

@ -1,5 +1,7 @@
#pragma once
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Mips/MipsCoprocessor0.hpp"
#include "Common/Types/Register/SizedWordRegister.hpp"
@ -124,7 +126,7 @@ public:
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(interrupts_masked),
CEREAL_NVP(operating_context),
CEREAL_NVP(count_interrupts_enabled),
CEREAL_NVP(count_interrupts_enabled)
);
}
};

7
liborbum/src/Resources/Ee/Core/EeCoreTlbEntry.hpp
View file

@ -1,8 +1,9 @@
#pragma once
/// Custom Mask type, provides useful cached values when constructed.
struct Mask
class Mask
{
public:
Mask(const uword pagemask = 0) :
pagemask(pagemask),
evenodd_mask(1 << 12),
@ -63,8 +64,9 @@ public:
/// See EE Core Users Manual page 120 - 123 about the TLB.
/// For the internal struct array below, index 0 corresponds to the Even
/// infomation, and index 1 correponds to the Odd information.
struct EeCoreTlbEntry
class EeCoreTlbEntry
{
public:
Mask mask;
uword vpn2;
bool g;
@ -90,6 +92,7 @@ struct EeCoreTlbEntry
}
} physical_info[2]; // Index 0 = Even, index 1 = Odd.
public:
template<class Archive>
void serialize(Archive & archive)
{

4
liborbum/src/Resources/Ee/Dmac/EeDmacChannelRegisters.hpp
View file

@ -1,5 +1,7 @@
#pragma once
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Register/SizedWordRegister.hpp"
#include "Common/Types/ScopeLock.hpp"
#include "Resources/Ee/Dmac/EeDmatag.hpp"
@ -79,7 +81,7 @@ public:
CEREAL_NVP(tag_exit),
CEREAL_NVP(tag_stall),
CEREAL_NVP(tag_irq),
CEREAL_NVP(dma_tag),
CEREAL_NVP(dma_tag)
);
}
};

44
liborbum/src/Resources/Ee/Dmac/EeDmacChannels.hpp
View file

@ -1,5 +1,7 @@
#pragma once
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/FifoQueue/DmaFifoQueue.hpp"
#include "Resources/Ee/Dmac/EeDmacChannelRegisters.hpp"
@ -47,6 +49,7 @@ public:
SizedWordRegister qwc;
EeDmacChannelRegister_Chcr_Ty chcr;
public:
template<class Archive>
void serialize(Archive & archive)
{
@ -70,6 +73,16 @@ public:
}
EeDmacChannelRegister_Addr tadr;
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
cereal::base_class<EeDmacChannel_Base<EeDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(tadr)
);
}
};
/// ASR EE DMAC channel, contains normal TADR registers plus ASR registers.
@ -83,6 +96,16 @@ public:
}
EeDmacChannelRegister_Addr asr[2];
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
cereal::base_class<EeDmacChannel_Tadr<EeDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(asr)
);
}
};
/// SADR EE DMAC channel, contains normal registers plus SADR register.
@ -96,6 +119,16 @@ public:
}
SizedWordRegister sadr;
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
cereal::base_class<EeDmacChannel_Base<EeDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(sadr)
);
}
};
/// TADR + SADR EE DMAC channel, contains normal registers plus TADR + SADR registers.
@ -110,4 +143,15 @@ public:
EeDmacChannelRegister_Addr tadr;
SizedWordRegister sadr;
public:
template<class Archive>
void serialize(Archive & archive)
{
archive(
cereal::base_class<EeDmacChannel_Base<EeDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(tadr),
CEREAL_NVP(sadr)
);
}
};

3
liborbum/src/Resources/Ee/Dmac/EeDmatag.hpp
View file

@ -5,8 +5,9 @@
/// An EE DMAtag type, as explained on page 58 of the EE Users Manual.
/// Although a DMAtag is 128-bit long, only the lower 2 x 32-bits are used (referred to as 64-bits in the map data below).
struct EeDmatag
class EeDmatag
{
public:
static constexpr Bitfield QWC = Bitfield(0, 16); // For tag0.
static constexpr Bitfield TAG = Bitfield(16, 16); // For tag0. Needed by CHCR register (all upper 16 bits).
static constexpr Bitfield PCE = Bitfield(26, 2); // For tag0.

1
liborbum/src/Resources/Ee/Dmac/REeDmac.hpp
View file

@ -57,6 +57,7 @@ public:
ArrayByteMemory memory_f530;
ArrayByteMemory memory_f5a0;
public:
template<class Archive>
void serialize(Archive & archive)
{

15
liborbum/src/Resources/Ee/EeRegisters.hpp
View file

@ -1,5 +1,9 @@
#pragma once
#include <cereal/access.hpp>
#include <cereal/types/polymorphic.hpp>
#include <cereal/types/string.hpp>
#include "Common/Options.hpp"
#include "Common/Types/Memory/ArrayByteMemory.hpp"
@ -38,9 +42,9 @@ public:
void serialize(Archive & archive)
{
archive(
cereal::base_class<SizedWordRegister>(this)
cereal::base_class<ArrayByteMemory>(this)
#if DEBUG_LOG_SIO_MESSAGES
,CEREAL_NVP(count)
,CEREAL_NVP(sio_buffer)
#endif
);
}
@ -73,8 +77,11 @@ public:
void serialize(Archive & archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
cereal::base_class<ArrayByteMemory>(this),
CEREAL_NVP(rdram_sdevid)
);
}
};
};
CEREAL_SPECIALIZE_FOR_ALL_ARCHIVES(EeRegister_Sio, cereal::specialization::member_serialize);
CEREAL_SPECIALIZE_FOR_ALL_ARCHIVES(EeRegister_Mch, cereal::specialization::member_serialize);

2
liborbum/src/Resources/Ee/Timers/EeTimersUnitRegisters.cpp
View file

@ -80,7 +80,7 @@ bool EeTimersUnitRegister_Mode::is_gate_hblnk_special()
return ((extract_field(CLKS) == 3) && (extract_field(GATS) == 0));
}
std::pair<uword, ControllerEventType> EeTimersUnitRegister_Mode::calculate_prescale_and_set_event()
std::pair<uword, ControllerEventType> EeTimersUnitRegister_Mode::get_properties()
{
uword source = extract_field(CLKS);
if (source == 0x0)

6
liborbum/src/Resources/Ee/Timers/EeTimersUnitRegisters.hpp
View file

@ -1,5 +1,7 @@
#pragma once
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Register/SizedWordRegister.hpp"
#include "Common/Types/ScopeLock.hpp"
#include "Controller/ControllerEvent.hpp"
@ -75,10 +77,10 @@ public:
/// Bus write latch. Signifies that the timer unit should be reset (ie: reset count with the prescale below).
bool write_latch;
/// Calculates unit parameters including:
/// Returns unit properties:
/// - The event source this timer follows.
/// - The prescale that should be set on the count register.
std::pair<uword, ControllerEventType> calculate_prescale_and_set_event();
std::pair<uword, ControllerEventType> get_properties();
public:
template<class Archive>

1
liborbum/src/Resources/Iop/Core/IopCoreCop0.hpp
View file

@ -42,6 +42,7 @@ public:
/// Array of COP0 registers.
SizedWordRegister* registers[Constants::IOP::IOPCore::COP0::NUMBER_REGISTERS];
public:
template<class Archive>
void serialize(Archive & archive)
{

2
liborbum/src/Resources/Iop/Core/IopCoreCop0Registers.hpp
View file

@ -1,5 +1,7 @@
#pragma once
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Mips/MipsCoprocessor0.hpp"
#include "Common/Types/Register/SizedWordRegister.hpp"

1
liborbum/src/Resources/Iop/Core/IopCoreR3000.hpp
View file

@ -31,6 +31,7 @@ public:
SizedWordRegister hi;
SizedWordRegister lo;
public:
template<class Archive>
void serialize(Archive & archive)
{

2
liborbum/src/Resources/Iop/Dmac/IopDmacChannelRegisters.hpp
View file

@ -1,5 +1,7 @@
#pragma once
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Register/SizedWordRegister.hpp"
#include "Common/Types/ScopeLock.hpp"
#include "Resources/Iop/Dmac/IopDmatag.hpp"

3
liborbum/src/Resources/Iop/Dmac/IopDmatag.hpp
View file

@ -5,8 +5,9 @@
/// An IOP DMAtag type, as explained by wisi and SP193's IOP DMA docs.
/// Although a DMAtag is 128-bit long, only the lower 2 x 32-bits are used (referred to as 64-bits in the map data below).
/// The other 64-bits are discarded upon reading the tag.
struct IopDmatag
class IopDmatag
{
public:
static constexpr Bitfield ADDR = Bitfield(0, 24); // For tag0.
static constexpr Bitfield IRQ = Bitfield(30, 1); // For tag0.
static constexpr Bitfield ERT = Bitfield(31, 1); // For tag0.

1
liborbum/src/Resources/Iop/Sio0/Sio0Registers.hpp
View file

@ -66,6 +66,7 @@ public:
/// depending on the different FIFO queue states (tx full/rx empty).
Sio0Register_Stat* stat;
public:
template<class Archive>
void serialize(Archive & archive)
{

2
liborbum/src/Resources/Iop/Sio2/Sio2PortRegisters.hpp
View file

@ -1,3 +1,5 @@
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Bitfield.hpp"
#include "Common/Types/Register/SizedWordRegister.hpp"
#include "Common/Types/ScopeLock.hpp"

4
liborbum/src/Resources/Iop/Sio2/Sio2Registers.hpp
View file

@ -1,5 +1,7 @@
#pragma once
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/FifoQueue/DmaFifoQueue.hpp"
#include "Common/Types/Register/ByteRegister.hpp"
#include "Common/Types/Register/SizedWordRegister.hpp"
@ -52,7 +54,7 @@ public:
CEREAL_NVP(transfer_port),
CEREAL_NVP(transfer_port_count),
CEREAL_NVP(transfer_direction),
CEREAL_NVP(write_latch),
CEREAL_NVP(write_latch)
);
}
};

9
liborbum/src/Resources/Iop/Timers/IopTimersUnitRegisters.cpp
View file

@ -117,7 +117,14 @@ void IopTimersUnitRegister_Mode::byte_bus_write_uword(const BusContext context,
write_latch = true;
}
std::pair<uword, ControllerEventType> IopTimersUnitRegister_Mode::calculate_prescale_and_event(const int unit_id)
bool IopTimersUnitRegister_Mode::is_enabled()
{
bool irq_on_of = extract_field(IopTimersUnitRegister_Mode::IRQ_ON_OF) > 0;
bool irq_on_target = extract_field(IopTimersUnitRegister_Mode::IRQ_ON_TARGET) > 0;
return irq_on_of || irq_on_target;
}
std::pair<uword, ControllerEventType> IopTimersUnitRegister_Mode::get_properties(const int unit_id)
{
if (unit_id < 0 || unit_id > 5)
throw std::runtime_error("Invalid IOP timer index to determine clock source!");

16
liborbum/src/Resources/Iop/Timers/IopTimersUnitRegisters.hpp
View file

@ -2,6 +2,8 @@
#include <utility>
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Register/SizedWordRegister.hpp"
#include "Common/Types/ScopeLock.hpp"
#include "Controller/ControllerEvent.hpp"
@ -83,18 +85,21 @@ public:
IopTimersUnitRegister_Mode();
/// When written to, caches timer event source and enabled status (looks at IRQ conditions).
/// Also resets the count register on write. Scope locked for the entire duration.
/// Sets the write latch, used to trigger resets/initialization.
void byte_bus_write_uhword(const BusContext context, const usize offset, const uhword value) override;
void byte_bus_write_uword(const BusContext context, const usize offset, const uword value) override;
/// Checks the IRQ conditions to see if this timer is "enabled"
/// (timer is only useful if an IRQ condition is set).
bool is_enabled();
/// Bus write latch. Signifies that the timer unit should be reset (ie: reset count with the prescale below).
bool write_latch;
/// Calculates unit parameters:
/// Returns unit properties:
/// - The event source this timer follows.
/// - The prescale that should be set on the count register.
std::pair<uword, ControllerEventType> calculate_prescale_and_event(const int unit_id);
std::pair<uword, ControllerEventType> get_properties(const int unit_id);
public:
template<class Archive>
@ -102,8 +107,7 @@ public:
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(write_latch),
CEREAL_NVP(event_type)
CEREAL_NVP(write_latch)
);
}
};

2
liborbum/src/Resources/Spu2/Spu2CoreRegisters.hpp
View file

@ -2,6 +2,8 @@
#include <cstddef>
#include <cereal/types/polymorphic.hpp>
#include "Common/Types/Bitfield.hpp"
#include "Common/Types/Register/SizedHwordRegister.hpp"
#include "Common/Types/ScopeLock.hpp"

2
utilities/src/Console.hpp
View file

@ -1,3 +1,5 @@
#pragma once
#include <string>
/// Prints a string to the console title bar.

2
utilities/src/Datetime.cpp
View file

@ -1,3 +1,5 @@
#include <stdexcept>
#include "Datetime.hpp"
std::string datetime_fmt(const char* format, const std::time_t datetime)

2
utilities/src/Datetime.hpp
View file

@ -1,3 +1,5 @@
#pragma once
#include <string>
#include <ctime>