Add in remainder of missing objects to serialize.

liborbum/src/Core.hpp

@@ -25,7 +25,7 @@
 #define CORE_API SHARED_IMPORT
 #endif
 
-struct RResources;
+class RResources;
 class CController;
 
 /// Core runtime options.

liborbum/src/Resources/Cdvd/CdvdRegisters.hpp

@@ -28,6 +28,7 @@ public:
     SizedByteRegister ready;
     DmaFifoQueue<> data_in;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {
@@ -58,4 +59,14 @@ public:
 
     /// Reference to the ready register.
     CdvdRegister_Ns_Rdy_Din* ns_rdy_din;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedByteRegister>(this),
+            CEREAL_NVP(write_latch)
+        );
+    }
 };

liborbum/src/Resources/Cdvd/RCdvd.hpp

@@ -17,8 +17,9 @@
 ///   This is set upon writing to the N_COMMAND register, where it also resets the INTR_STAT.CmdComplete bit. Use this in order to step the state within the emulator.
 ///   INTR_STAT.CmdComplete is set upon completion, and the IOP.INTC.CDROM bit is set.
 /// - N_2005 needs to be set to 0x4E upon boot (ready), seems to use 0x40 after that, or 0x0 if not ready...
-struct RCdvd
+class RCdvd
 {
+public:
     RCdvd();
 
     /// CDVD Registers.
@@ -64,6 +65,7 @@ struct RCdvd
     /// CDVD RTC state.
     CdvdRtc rtc;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Core/EeCoreCop0.hpp

@@ -74,6 +74,7 @@ public:
     /// Array of PCR0/PCR1, used by the MFPC/MTPC instructions.
     SizedWordRegister* pcr_registers[Constants::EE::EECore::COP0::NUMBER_PCR_REGISTERS];
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Core/EeCoreCop0Registers.hpp

@@ -115,6 +115,18 @@ private:
 
     /// Updates the count interrupt state.
     void handle_count_interrupt_state_update();
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(interrupts_masked),
+            CEREAL_NVP(operating_context),
+            CEREAL_NVP(count_interrupts_enabled),
+        );
+    }
 };
 
 /// Cause register.
@@ -149,6 +161,16 @@ public:
 private:
     /// IRQ line flags.
     bool irq_lines[8];
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(irq_lines)
+        );
+    }
 };
 
 class EeCoreCop0Register_Prid : public SizedWordRegister

liborbum/src/Resources/Ee/Core/EeCoreFpu.hpp

@@ -37,6 +37,7 @@ public:
     /// Pointer to the EE Core COP0 coprocessor, needed for the Status register.
     EeCoreCop0* cop0;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Core/EeCoreR5900.hpp

@@ -38,6 +38,7 @@ public:
     /// See the EE Core instruction QFSRV for more details (SA is only used for this instruction).
     SizedWordRegister sa;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Core/EeCoreTlbEntry.hpp

@@ -45,6 +45,7 @@ struct Mask
     uword evenodd_mask;
     uword tlb_mask;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {
@@ -98,8 +99,7 @@ struct EeCoreTlbEntry
             CEREAL_NVP(g),
             CEREAL_NVP(asid),
             CEREAL_NVP(s),
-            CEREAL_NVP(physical_info[0]),
-            CEREAL_NVP(physical_info[1])
+            CEREAL_NVP(physical_info)
         );
     }
 };

liborbum/src/Resources/Ee/Core/REeCore.hpp

@@ -9,8 +9,9 @@
 /// REeCore declares the R5900 structure, co-processors, etc, forming the EE Core.
 /// For reference documentation, see the EE Core Users Manual (SCE).
 /// VU0 is attached to the EE Core as COP2, declared separately from here.
-struct REeCore
+class REeCore
 {
+public:
     REeCore();
 
     /// R5900 CPU.
@@ -28,6 +29,7 @@ struct REeCore
     /// Scratchpad memory.
     ArrayByteMemory scratchpad_memory;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Dmac/EeDmacChannelRegisters.hpp

@@ -68,6 +68,20 @@ public:
     /// DMAtag holder, contains the current dma tag read, set by the DMAC.
     /// TODO: might be a way to omit this and just use the upper 16-bits, but for now extra information is required.
     EeDmatag dma_tag;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(dma_started),
+            CEREAL_NVP(tag_exit),
+            CEREAL_NVP(tag_stall),
+            CEREAL_NVP(tag_irq),
+            CEREAL_NVP(dma_tag),
+        );
+    }
 };
 
 /// DMAC ADDR (made up) register, used by the MADR, TADR and ASR registers.

liborbum/src/Resources/Ee/Dmac/EeDmatag.hpp

@@ -74,4 +74,14 @@ struct EeDmatag
     /// tag1 is for bits 32-63.
     uword tag0;
     uword tag1;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            CEREAL_NVP(tag0),
+            CEREAL_NVP(tag1)
+        );
+    }
 };

liborbum/src/Resources/Ee/Dmac/REeDmac.hpp

@@ -6,8 +6,9 @@
 #include "Resources/Ee/Dmac/EeDmacRegisters.hpp"
 
 /// EE DMAC Resources. See page 41 onwards of the EE Users Manual.
-struct REeDmac
+class REeDmac
 {
+public:
     REeDmac();
 
     /// DMA Channels. See page 42 of the EE Users Manual.

liborbum/src/Resources/Ee/EeRegisters.hpp

@@ -32,6 +32,18 @@ private:
     static constexpr const char* SIO_BUFFER_PREFIX = "EE SIO Message";
     std::string sio_buffer;
 #endif
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this)
+#if DEBUG_LOG_SIO_MESSAGES
+            ,CEREAL_NVP(count)
+#endif
+        );
+    }
 };
 
 /// The MCH register class. No information available except for old PCSX2's code.
@@ -55,4 +67,14 @@ private:
     // Variables below needed by logic. Used by the BIOS to initialize/test the RDRAM. See old PCSX2 code (Hw.h/HwRead.cpp/HwWrite.cpp).
     int rdram_sdevid = 0;
     static constexpr int rdram_devices = 2; // Put 8 for TOOL and 2 for PS2 and PSX.
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(rdram_sdevid)
+        );
+    }
 };

liborbum/src/Resources/Ee/Gif/RGif.hpp

@@ -3,8 +3,9 @@
 #include "Common/Types/Memory/ArrayByteMemory.hpp"
 #include "Common/Types/Register/SizedWordRegister.hpp"
 
-struct RGif
+class RGif
 {
+public:
     RGif();
 
     /// GIF memory mapped registers. See page 21 of EE Users Manual.
@@ -21,6 +22,7 @@ struct RGif
     SizedWordRegister p3tag;
     ArrayByteMemory memory_30b0;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Intc/REeIntc.hpp

@@ -3,8 +3,9 @@
 #include "Common/Types/Memory/ArrayByteMemory.hpp"
 #include "Resources/Ee/Intc/EeIntcRegisters.hpp"
 
-struct REeIntc
+class REeIntc
 {
+public:
     REeIntc();
 
     /// EE INTC memory mapped registers. See page 24 of EE Users Manual.
@@ -12,6 +13,7 @@ struct REeIntc
     EeIntcRegister_Stat stat;
     ArrayByteMemory memory_f020;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Ipu/RIpu.hpp

@@ -5,8 +5,9 @@
 #include "Common/Types/Register/SizedWordRegister.hpp"
 #include "Resources/Ee/Ipu/IpuRegisters.hpp"
 
-struct RIpu
+class RIpu
 {
+public:
     RIpu();
 
     /// IPU memory mapped registers. See page 21 of EE Users Manual.
@@ -17,6 +18,7 @@ struct RIpu
     IpuRegister_Top top;
     ArrayByteMemory memory_2040;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/REe.hpp

@@ -57,6 +57,7 @@ public:
     EeRegister_Mch memory_mch; // No documentation (except for name)! From old PCSX2. Needed by the BIOS for RDRAM initialisation.
     ArrayByteMemory memory_f450;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Timers/EeTimersUnitRegisters.cpp

@@ -50,8 +50,7 @@ void EeTimersUnitRegister_Count::reset_prescale(const int prescale_target)
 }
 
 EeTimersUnitRegister_Mode::EeTimersUnitRegister_Mode() :
-    write_latch(false),
-    event_type(ControllerEventType::Time)
+    write_latch(false)
 {
 }
 
@@ -81,28 +80,24 @@ bool EeTimersUnitRegister_Mode::is_gate_hblnk_special()
     return ((extract_field(CLKS) == 3) && (extract_field(GATS) == 0));
 }
 
-uword EeTimersUnitRegister_Mode::calculate_prescale_and_set_event()
+std::pair<uword, ControllerEventType> EeTimersUnitRegister_Mode::calculate_prescale_and_set_event()
 {
     uword source = extract_field(CLKS);
     if (source == 0x0)
     {
-        event_type = ControllerEventType::Time;
-        return 1;
+        return std::make_pair(1, ControllerEventType::Time);
     }
     else if (source == 0x1)
     {
-        event_type = ControllerEventType::Time;
-        return 16;
+        return std::make_pair(16, ControllerEventType::Time);
     }
     else if (source == 0x2)
     {
-        event_type = ControllerEventType::Time;
-        return 256;
+        return std::make_pair(256, ControllerEventType::Time);
     }
     else if (source == 0x3)
     {
-        event_type = ControllerEventType::HBlank;
-        return 1;
+        return std::make_pair(1, ControllerEventType::HBlank);
     }
     else
     {

liborbum/src/Resources/Ee/Timers/EeTimersUnitRegisters.hpp

@@ -32,6 +32,18 @@ private:
     /// (ie: needs x amount before 1 is added to the count).
     int prescale_target;
     int prescale_count;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(is_overflowed),
+            CEREAL_NVP(prescale_target),
+            CEREAL_NVP(prescale_count)
+        );
+    }
 };
 
 /// The Timer Mode register type. See EE Users Manual page 36.
@@ -64,10 +76,17 @@ public:
     bool write_latch;
 
     /// Calculates unit parameters including:
-    /// - Internally sets the event source this timer follows.
-    /// - Returns the prescale that should be set on the count register.
-    uword calculate_prescale_and_set_event();
+    /// - The event source this timer follows.
+    /// - The prescale that should be set on the count register.
+    std::pair<uword, ControllerEventType> calculate_prescale_and_set_event();
 
-    /// Holds the cached result of which event type this timer is following.
-    ControllerEventType event_type;
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(write_latch)
+        );
+    }
 };

liborbum/src/Resources/Ee/Timers/EeTimersUnits.hpp

@@ -31,6 +31,7 @@ public:
     EeTimersUnitRegister_Mode mode;
     SizedWordRegister compare;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {
@@ -49,4 +50,14 @@ public:
     EeTimersUnit_Hold(const int unit_id);
 
     SizedWordRegister hold;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<EeTimersUnit_Base>(this),
+            CEREAL_NVP(hold)
+        );
+    }
 };

liborbum/src/Resources/Ee/Timers/REeTimers.hpp

@@ -5,8 +5,9 @@
 
 /// The EE Timers resources.
 /// Defines the 4 timers within the EE, as listed on page 33 onwards of the EE Users Manual.
-struct REeTimers
+class REeTimers
 {
+public:
     REeTimers();
 
     EeTimersUnit_Hold unit_0;
@@ -17,6 +18,7 @@ struct REeTimers
     /// Timer abstractions.
     EeTimersUnit units[Constants::EE::Timers::NUMBER_TIMERS];
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Vpu/RVpu.hpp

@@ -17,6 +17,7 @@ public:
     /// VU structure.
     RVu vu;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Vpu/Vif/VifUnits.hpp

@@ -40,11 +40,11 @@ public:
     VifUnitRegister_Fbrst fbrst;
     VifUnitRegister_Err err;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {
         archive(
-            CEREAL_NVP(core_id),
             CEREAL_NVP(r0),
             CEREAL_NVP(r1),
             CEREAL_NVP(r2),

liborbum/src/Resources/Ee/Vpu/Vu/RVu.hpp

@@ -18,6 +18,7 @@ public:
     /// Shared VU registers.
     VuRegister_Fbrst fbrst;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Ee/Vpu/Vu/VuUnits.hpp

@@ -73,11 +73,13 @@ public:
     /// Used by different things, eg: ccr registers for VU0 and bus mappings for VU1.
     MapperHwordWordRegister vi_32[Constants::EE::VPU::VU::NUMBER_VI_REGISTERS];
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {
         archive(
-            CEREAL_NVP(core_id),
+            CEREAL_NVP(vf),
+            CEREAL_NVP(vi),
             CEREAL_NVP(acc),
             CEREAL_NVP(i),
             CEREAL_NVP(q),
@@ -115,6 +117,17 @@ public:
 
     /// Reference to the EE Core COP0 coprocessor, needed for the Status register.
     EeCoreCop0* cop0;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<VuUnit_Base>(this),
+            CEREAL_NVP(memory_micro),
+            CEREAL_NVP(memory_mem)
+        );
+    }
 };
 
 /// Represents VU1.
@@ -126,4 +139,15 @@ public:
     /// VU memory, defined on page 18 of the VU Users Manual.
     ArrayByteMemory memory_micro; // 16 KiB.
     ArrayByteMemory memory_mem;   // 16 KiB.
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<VuUnit_Base>(this),
+            CEREAL_NVP(memory_micro),
+            CEREAL_NVP(memory_mem)
+        );
+    }
 };

liborbum/src/Resources/Gs/RGs.hpp

@@ -45,6 +45,7 @@ public:
     // 0x12002000.
     ArrayByteMemory memory_2000;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Iop/Core/IopCoreCop0Registers.hpp

@@ -67,6 +67,17 @@ private:
     /// Updates the operation context state.
     /// Uses the KSU, ERL and EXL bits.
     void handle_operating_context_update();
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(interrupts_masked),
+            CEREAL_NVP(operating_context)
+        );
+    }
 };
 
 /// Cause register of the IOP COP0.
@@ -95,6 +106,16 @@ public:
 private:
     /// IRQ line flags.
     bool irq_lines[8];
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(irq_lines)
+        );
+    }
 };
 
 /// The PRId register of the IOP COP0.

liborbum/src/Resources/Iop/Core/RIopCore.hpp

@@ -4,8 +4,9 @@
 #include "Resources/Iop/Core/IopCoreCop0.hpp"
 #include "Resources/Iop/Core/IopCoreR3000.hpp"
 
-struct RIopCore
+class RIopCore
 {
+public:
     RIopCore();
 
     /// R3000 CPU.
@@ -17,6 +18,7 @@ struct RIopCore
     /// Scratchpad memory (1KB). Allocated at 0x1F800000.
     ArrayByteMemory scratchpad_memory;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Iop/Dmac/IopDmacChannelRegisters.hpp

@@ -62,6 +62,17 @@ public:
 
     // DMA tag holding area, set by the DMAC when a tag is read.
     IopDmatag dma_tag;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(dma_started),
+            CEREAL_NVP(dma_tag)
+        );
+    }
 };
 
 /// The IOP DMAC D_BCR register.
@@ -86,6 +97,16 @@ public:
     // The register value is not meant to change during the transfer.
     // This is directly accessible to the IOP DMAC which manipulates this value.
     size_t transfer_length;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(transfer_length)
+        );
+    }
 };
 
 // A base IOP TO DMAC D_CHCR register.

liborbum/src/Resources/Iop/Dmac/IopDmatag.hpp

@@ -56,4 +56,14 @@ struct IopDmatag
     /// tag1 is for bits 32-63.
     uword tag0;
     uword tag1;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            CEREAL_NVP(tag0),
+            CEREAL_NVP(tag1)
+        );
+    }
 };

liborbum/src/Resources/Iop/Dmac/RIopDmac.hpp

@@ -8,8 +8,9 @@
 
 /// IOP DMAC resources.
 /// See the no$psx docs and wisi and SP193's DMA docs for information.
-struct RIopDmac
+class RIopDmac
 {
+public:
     RIopDmac();
 
     /// DMAC Common Registers.
@@ -41,6 +42,7 @@ struct RIopDmac
     /// There are 14 channels in total (to make it even), with the last one being undefined.
     IopDmacChannel channels[Constants::IOP::DMAC::NUMBER_DMAC_CHANNELS - 1];
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Iop/Intc/RIopIntc.hpp

@@ -3,12 +3,14 @@
 #include "Resources/Iop/Intc/IopIntcRegisters.hpp"
 
 /// IOP INTC resources.
-struct RIopIntc
+class RIopIntc
 {
+public:
     IopIntcRegister_Ctrl ctrl;
     IopIntcRegister_Mask mask;
     IopIntcRegister_Stat stat;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Iop/RIop.hpp

@@ -17,8 +17,9 @@
 /// some online resources exist for the PS1 which can help with certain parts, but
 /// otherwise it has been reversed engineered. Big props to PCSX2 and No$PSX docs -
 /// most of the implementation is based off their work.
-struct RIop
+class RIop
 {
+public:
     RIop();
 
     /// Sub resources.
@@ -67,6 +68,7 @@ struct RIop
     SizedWordRegister register_2070;
     SizedWordRegister register_3800;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Iop/Sio0/RSio0.hpp

@@ -5,13 +5,15 @@
 
 /// SIO0 resources.
 /// Responsible for communication with controllers and memory cards.
-struct RSio0
+class RSio0
 {
+public:
     Sio0Register_Data data; // Hybrid FIFO port - can read and write to this port simultaneously.
     Sio0Register_Stat stat;
     SizedHwordRegister mode;
     Sio0Register_Ctrl ctrl;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Iop/Sio0/Sio0Registers.hpp

@@ -41,6 +41,7 @@ public:
     /// Scope locked bus writes.
     void byte_bus_write_uhword(const BusContext context, const usize offset, const uhword value) override;
 };
+
 /// SIO0 data "register".
 /// This is a hybrid FIFO port, where writing and reading access 2 different
 /// FIFO queues. Tx direction means from SIO2 to SIO0, Rx direction means from

liborbum/src/Resources/Iop/Sio2/RSio2.hpp

@@ -10,8 +10,9 @@
 /// Responsible for communication with controllers and memory cards.
 /// "SIO2 is a DMA interface for the SIO" - IopHW.h from PCSX2. See also IopSio2.h/cpp.
 /// A lot of information can be found through the PS2SDK too: https://github.com/ps2dev/ps2sdk/tree/master/iop/system/sio2log/src.
-struct RSio2
+class RSio2
 {
+public:
     RSio2();
 
     /// SIO2 ports (16 total).
@@ -42,6 +43,7 @@ struct RSio2
     SizedWordRegister register_827c;
     SizedWordRegister intr; // Also known as the STAT register.
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Iop/Sio2/Sio2PortRegisters.hpp

@@ -33,4 +33,15 @@ public:
 
     /// Scope locked bus writes.
     void byte_bus_write_uword(const BusContext context, const usize offset, const uword value) override;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(write_latch),
+            CEREAL_NVP(port_transfer_started)
+        );
+    }
 };

liborbum/src/Resources/Iop/Sio2/Sio2Registers.hpp

@@ -41,4 +41,18 @@ public:
 
     /// Write latch, set to true on bus write, cleared by the controller.
     bool write_latch;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(transfer_started),
+            CEREAL_NVP(transfer_port),
+            CEREAL_NVP(transfer_port_count),
+            CEREAL_NVP(transfer_direction),
+            CEREAL_NVP(write_latch),
+        );
+    }
 };

liborbum/src/Resources/Iop/Timers/IopTimersUnitRegisters.cpp

@@ -84,9 +84,7 @@ void IopTimersUnitRegister_Count::increment_32(const uword value)
 }
 
 IopTimersUnitRegister_Mode::IopTimersUnitRegister_Mode() :
-    write_latch(false),
-    is_enabled(false),
-    event_type(ControllerEventType::Time)
+    write_latch(false)
 {
 }
 
@@ -119,7 +117,7 @@ void IopTimersUnitRegister_Mode::byte_bus_write_uword(const BusContext context,
     write_latch = true;
 }
 
-uword IopTimersUnitRegister_Mode::calculate_prescale_and_set_event(const int unit_id)
+std::pair<uword, ControllerEventType> IopTimersUnitRegister_Mode::calculate_prescale_and_event(const int unit_id)
 {
     if (unit_id < 0 || unit_id > 5)
         throw std::runtime_error("Invalid IOP timer index to determine clock source!");
@@ -136,13 +134,11 @@ uword IopTimersUnitRegister_Mode::calculate_prescale_and_set_event(const int uni
         {
             if (extract_field(EVENT_SRC) == 0)
             {
-                event_type = ControllerEventType::Time;
-                return 1;
+                return std::make_pair(1, ControllerEventType::Time);
             }
             else
             {
-                event_type = ControllerEventType::HBlank;
-                return 1;
+                return std::make_pair(1, ControllerEventType::HBlank);
             }
         }
     }
@@ -157,8 +153,7 @@ uword IopTimersUnitRegister_Mode::calculate_prescale_and_set_event(const int uni
         {
             if (extract_field(EVENT_SRC) == 0)
             {
-                event_type = ControllerEventType::Time;
-                return 1;
+                return std::make_pair(1, ControllerEventType::Time);
             }
             else
             {

liborbum/src/Resources/Iop/Timers/IopTimersUnitRegisters.hpp

@@ -1,5 +1,7 @@
 #pragma once
 
+#include <utility>
+
 #include "Common/Types/Register/SizedWordRegister.hpp"
 #include "Common/Types/ScopeLock.hpp"
 #include "Controller/ControllerEvent.hpp"
@@ -41,6 +43,18 @@ private:
     /// (ie: needs x amount before 1 is added to the count).
     int prescale_target;
     int prescale_count;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(is_overflowed),
+            CEREAL_NVP(prescale_target),
+            CEREAL_NVP(prescale_count)
+        );
+    }
 };
 
 /// The Timer Mode register type.
@@ -77,15 +91,19 @@ public:
     /// Bus write latch. Signifies that the timer unit should be reset (ie: reset count with the prescale below).
     bool write_latch;
 
-    /// Holds the cached result of if the timer is enabled, based on the interrupt bits set.
-    /// Used as a way to increase performance by skipping over useless timers.
-    bool is_enabled;
+    /// Calculates unit parameters:
+    /// - The event source this timer follows.
+    /// - The prescale that should be set on the count register.
+    std::pair<uword, ControllerEventType> calculate_prescale_and_event(const int unit_id);
 
-    /// Calculates unit parameters including:
-    /// - Internally sets the event source this timer follows.
-    /// - Returns the prescale that should be set on the count register.
-    uword calculate_prescale_and_set_event(const int unit_id);
-
-    /// Holds the cached result of which event type this timer is following.
-    ControllerEventType event_type;
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedWordRegister>(this),
+            CEREAL_NVP(write_latch),
+            CEREAL_NVP(event_type)
+        );
+    }
 };

liborbum/src/Resources/Iop/Timers/IopTimersUnits.hpp

@@ -16,11 +16,11 @@ public:
     IopTimersUnitRegister_Mode mode;
     SizedWordRegister compare;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {
         archive(
-            CEREAL_NVP(unit_id),
             CEREAL_NVP(count),
             CEREAL_NVP(mode),
             CEREAL_NVP(compare)

liborbum/src/Resources/Iop/Timers/RIopTimers.hpp

@@ -4,8 +4,9 @@
 #include "Resources/Iop/Timers/IopTimersUnits.hpp"
 
 /// IOP timers.
-struct RIopTimers
+class RIopTimers
 {
+public:
     RIopTimers();
 
     /// Contains 16-bit (0 -> 2) and 32-bit (3 -> 5) timers.
@@ -19,6 +20,7 @@ struct RIopTimers
     /// Timer abstractions.
     IopTimersUnit_Base* units[Constants::IOP::Timers::NUMBER_TIMERS];
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/RResources.hpp

@@ -16,8 +16,9 @@
 /// PS2 Resources state.
 /// Some resources have dependencies which need to be initialised after the
 /// resources have been created - you will need to manually call initialize().
-struct RResources
+class RResources
 {
+public:
     RResources();
 
     /// Sub-components.
@@ -71,6 +72,7 @@ struct RResources
     DmaFifoQueue<> fifo_fromsio2;
     DmaFifoQueue<> fifo_tosio2;
 
+public:
     template<class Archive>
     void serialize(Archive& archive)
     {

liborbum/src/Resources/Spu2/RSpu2.hpp

@@ -10,8 +10,9 @@
 /// No official documentation, except for the SPU2 Overview manual which does help.
 /// Most of the implementation comes from PCSX2. Thanks to everyone involved!
 /// The registers are assigned to the 0x1F900000 -> 0x1F900800 space in the IOP.
-struct RSpu2
+class RSpu2
 {
+public:
     RSpu2();
 
     /// SPU2 Cores.
@@ -41,6 +42,7 @@ struct RSpu2
     ArrayByteMemory memory_07b0;
     ArrayByteMemory memory_07ce;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Spu2/Spu2CoreConstants.hpp

@@ -15,8 +15,8 @@ struct Spu2CoreConstants
     };
 
     static constexpr Spu2CoreInfo SPU2_STATIC_INFO[Constants::SPU2::NUMBER_CORES] =
-        {
-            {0x2000, 0x2200},
-            {0x2400, 0x2600},
+    {
+        {0x2000, 0x2200},
+        {0x2400, 0x2600}
     };
 };

liborbum/src/Resources/Spu2/Spu2CoreRegisters.hpp

@@ -93,6 +93,16 @@ public:
     /// Current auto/manual DMA transfer count state, in terms of hwords.
     /// Reset upon the register being written to.
     size_t dma_offset;
+
+public:
+    template<class Archive>
+    void serialize(Archive & archive)
+    {
+        archive(
+            cereal::base_class<SizedHwordRegister>(this),
+            CEREAL_NVP(dma_offset)
+        );
+    }
 };
 
 /// SPU2 Core STATX register.

liborbum/src/Resources/Spu2/Spu2CoreVoice.hpp

@@ -22,6 +22,7 @@ public:
     SizedHwordRegister naxh;
     SizedHwordRegister naxl;
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {

liborbum/src/Resources/Spu2/Spu2Cores.hpp

@@ -145,11 +145,11 @@ public:
     Spu2CoreVoice voice_23;
     Spu2CoreVoice* voices[Constants::SPU2::NUMBER_CORE_VOICES];
 
+public:
     template<class Archive>
     void serialize(Archive & archive)
     {
         archive(
-            CEREAL_NVP(core_id),
             CEREAL_NVP(pmon0),
             CEREAL_NVP(pmon1),
             CEREAL_NVP(non0),