mirror of
https://github.com/hch12907/orbum.git
synced 2024-06-02 19:38:16 -04:00
Fixed up minor error with SPU2 interrupts.
This commit is contained in:
Marco Satti
parent
ab51de1680
commit
f634a14c5f
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@ -21,15 +21,15 @@ bool FIFOQueue_t::readByte(const Context_t context, u8 & data)
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if (mDebugReads)
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{
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#if DEBUG_LOG_VALUE_AS_HEX
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log(Debug, "%s: %s Read u8 (S = %d), Used Size = %d, Value = 0x%X.", DEBUG_CONTEXT_STRINGS[context], mMnemonic.c_str(), success, mFIFOQueue.read_available(), data);
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log(Debug, "%s: %s Read u8 (Ok = %d), Used Size = %d, Value = 0x%X.", DEBUG_CONTEXT_STRINGS[context], mMnemonic.c_str(), success, getReadAvailable(), data);
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#else
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log(Debug, "%s: %s Read u8 (S = %d), Used Size = %d, Value = %d.", SYSTEM_STR[context], mMnemonic.c_str(), success, mFIFOQueue.read_available(), data);
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log(Debug, "%s: %s Read u8 (Ok = %d), Used Size = %d, Value = %d.", SYSTEM_STR[context], mMnemonic.c_str(), success, getReadAvailable(), data);
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#endif
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}
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#endif
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if (!success)
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log(Debug, "FIFOQueue_t: Failed to push a byte to the FIFO queue. This **might** be ok, but you have been warned...");
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log(Debug, "FIFOQueue_t: Failed to read a byte to the FIFO queue. This **might** be ok, but you have been warned...");
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return success;
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}
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@ -42,9 +42,9 @@ bool FIFOQueue_t::writeByte(const Context_t context, const u8 data)
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if (mDebugWrites)
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{
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#if DEBUG_LOG_VALUE_AS_HEX
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log(Debug, "%s: %s Write u8 (S = %d), Free Size = %d, Value = 0x%X.", DEBUG_CONTEXT_STRINGS[context], mMnemonic.c_str(), success, mFIFOQueue.write_available(), data);
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log(Debug, "%s: %s Write u8 (Ok = %d), Used Size = %d, Value = 0x%X.", DEBUG_CONTEXT_STRINGS[context], mMnemonic.c_str(), success, getReadAvailable(), data);
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#else
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log(Debug, "%s: %s Write u8 (S = %d), Free Size = %d, Value = %d.", SYSTEM_STR[context], mMnemonic.c_str(), success, mFIFOQueue.write_available(), data);
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log(Debug, "%s: %s Write u8 (Ok = %d), Used Size = %d, Value = %d.", SYSTEM_STR[context], mMnemonic.c_str(), success, getReadAvailable(), data);
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#endif
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}
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#endif
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@ -7,8 +7,8 @@
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CDVD_t::CDVD_t() :
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N_COMMAND(std::make_shared<CDVDRegister_NS_COMMAND_t>("CDVD N_COMMAND", true, true)),
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N_RDY_DIN(std::make_shared<CDVDRegister_NS_RDY_DIN_t>("CDVD N_READY", "CDVD N_DATA_IN", false, false, 16)),
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N_DATA_OUT(std::make_shared<CDVDFIFOQueue_NS_DATA_OUT_t>("CDVD N_DATA_OUT", false, false, 16, N_RDY_DIN)),
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N_RDY_DIN(std::make_shared<CDVDRegister_NS_RDY_DIN_t>("CDVD N_READY", "CDVD N_DATA_IN", true, true, 16)),
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N_DATA_OUT(std::make_shared<CDVDFIFOQueue_NS_DATA_OUT_t>("CDVD N_DATA_OUT", true, true, 16, N_RDY_DIN)),
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BREAK(std::make_shared<Register8_t>("CDVD BREAK", true, true)),
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INTR_STAT(std::make_shared<Register8_t>("CDVD INTR_STAT", true, true)),
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STATUS(std::make_shared<Register8_t>("CDVD STATUS", true, true)),
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@ -19,9 +19,9 @@ CDVD_t::CDVD_t() :
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TYPE(std::make_shared<Register8_t>("CDVD TYPE", true, true)),
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REGISTER_2013(std::make_shared<Register8_t>("CDVD REGISTER_2013", true, true)),
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RSV(std::make_shared<Register8_t>("CDVD RSV", true, true)),
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S_COMMAND(std::make_shared<CDVDRegister_NS_COMMAND_t>("CDVD S_COMMAND", false, false)),
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S_RDY_DIN(std::make_shared<CDVDRegister_NS_RDY_DIN_t>("CDVD S_READY", "CDVD S_DATA_IN", false, false, 16)),
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S_DATA_OUT(std::make_shared<CDVDFIFOQueue_NS_DATA_OUT_t>("CDVD S_DATA_OUT", false, false, 16, S_RDY_DIN)),
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S_COMMAND(std::make_shared<CDVDRegister_NS_COMMAND_t>("CDVD S_COMMAND", true, false)),
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S_RDY_DIN(std::make_shared<CDVDRegister_NS_RDY_DIN_t>("CDVD S_READY", "CDVD S_DATA_IN", true, true, 16)),
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S_DATA_OUT(std::make_shared<CDVDFIFOQueue_NS_DATA_OUT_t>("CDVD S_DATA_OUT", true, true, 16, S_RDY_DIN)),
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KEY_20(std::make_shared<Register8_t>("CDVD KEY_20", true, true)),
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KEY_21(std::make_shared<Register8_t>("CDVD KEY_21", true, true)),
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KEY_22(std::make_shared<Register8_t>("CDVD KEY_22", true, true)),
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@ -124,7 +124,7 @@ public:
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};
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/*
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Represents IOP DMAC channel 5 - PIO (parallel I/O?) channel.
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Represents IOP DMAC channel 5 - PIO (parallel I/O) channel.
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This channel inherits a base IOP DMAC channel.
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*/
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class IOPDmacChannel_PIO_t : public IOPDmacChannel_t
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@ -138,7 +138,7 @@ public:
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/*
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Represents IOP DMAC channel 6 - the OTClear channel.
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The OTClear channel inherits a base IOP DMAC channel.
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TODO: what is this???
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TODO: Ordering table clear - related to PSX GPU. Probably don't have to worry about for now.
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*/
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class IOPDmacChannel_OTClear_t : public IOPDmacChannel_t
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{
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@ -37,29 +37,29 @@ IOPDmacRegister_PCR0_t::IOPDmacRegister_PCR0_t(const char * mnemonic, const bool
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IOPDmacRegister_ICR0_t::IOPDmacRegister_ICR0_t(const char * mnemonic, const bool debugReads, const bool debugWrites) :
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BitfieldRegister32_t(mnemonic, debugReads, debugWrites)
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{
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registerField(Fields::IRM0, "IRM0", 0, 1, 0);
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registerField(Fields::IRM1, "IRM1", 1, 1, 0);
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registerField(Fields::IRM2, "IRM2", 2, 1, 0);
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registerField(Fields::IRM3, "IRM3", 3, 1, 0);
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registerField(Fields::IRM4, "IRM4", 4, 1, 0);
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registerField(Fields::IRM5, "IRM5", 5, 1, 0);
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registerField(Fields::IRM6, "IRM6", 6, 1, 0);
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registerField(Fields::IRM0, "IRM0 (fromMDEC)", 0, 1, 0);
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registerField(Fields::IRM1, "IRM1 (toMDEC)", 1, 1, 0);
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registerField(Fields::IRM2, "IRM2 (SIF2/GPU)", 2, 1, 0);
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registerField(Fields::IRM3, "IRM3 (CDROM)", 3, 1, 0);
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registerField(Fields::IRM4, "IRM4 (SPU2c0)", 4, 1, 0);
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registerField(Fields::IRM5, "IRM5 (PIO)", 5, 1, 0);
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registerField(Fields::IRM6, "IRM6 (OTClear)", 6, 1, 0);
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registerField(Fields::Error, "Error", 15, 1, 0);
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registerField(Fields::TCM0, "TCM0", 16, 1, 0);
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registerField(Fields::TCM1, "TCM1", 17, 1, 0);
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registerField(Fields::TCM2, "TCM2", 18, 1, 0);
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registerField(Fields::TCM3, "TCM3", 19, 1, 0);
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registerField(Fields::TCM4, "TCM4", 20, 1, 0);
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registerField(Fields::TCM5, "TCM5", 21, 1, 0);
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registerField(Fields::TCM6, "TCM6", 22, 1, 0);
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registerField(Fields::TCM0, "TCM0 (fromMDEC)", 16, 1, 0);
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registerField(Fields::TCM1, "TCM1 (toMDEC)", 17, 1, 0);
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registerField(Fields::TCM2, "TCM2 (SIF2/GPU)", 18, 1, 0);
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registerField(Fields::TCM3, "TCM3 (CDROM)", 19, 1, 0);
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registerField(Fields::TCM4, "TCM4 (SPU2c0)", 20, 1, 0);
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registerField(Fields::TCM5, "TCM5 (PIO)", 21, 1, 0);
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registerField(Fields::TCM6, "TCM6 (OTClear)", 22, 1, 0);
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registerField(Fields::MasterEnable, "MasterEnable", 23, 1, 0);
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registerField(Fields::TCI0, "TCI0", 24, 1, 0);
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registerField(Fields::TCI1, "TCI1", 25, 1, 0);
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registerField(Fields::TCI2, "TCI2", 26, 1, 0);
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registerField(Fields::TCI3, "TCI3", 27, 1, 0);
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registerField(Fields::TCI4, "TCI4", 28, 1, 0);
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registerField(Fields::TCI5, "TCI5", 29, 1, 0);
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registerField(Fields::TCI6, "TCI6", 30, 1, 0);
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registerField(Fields::TCI0, "TCI0 (fromMDEC)", 24, 1, 0);
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registerField(Fields::TCI1, "TCI1 (toMDEC)", 25, 1, 0);
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registerField(Fields::TCI2, "TCI2 (SIF2/GPU)", 26, 1, 0);
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registerField(Fields::TCI3, "TCI3 (CDROM)", 27, 1, 0);
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registerField(Fields::TCI4, "TCI4 (SPU2c0)", 28, 1, 0);
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registerField(Fields::TCI5, "TCI5 (PIO)", 29, 1, 0);
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registerField(Fields::TCI6, "TCI6 (OTClear)", 30, 1, 0);
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registerField(Fields::MasterInterrupt, "MasterInterrupt", 31, 1, 0);
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}
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@ -112,34 +112,34 @@ IOPDmacRegister_ICR1_t::IOPDmacRegister_ICR1_t(const char * mnemonic, const bool
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BitfieldRegister32_t(mnemonic, debugReads, debugWrites),
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mICR0(ICR0)
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{
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registerField(Fields::IQE0, "IQE0", 0, 1, 0);
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registerField(Fields::IQE1, "IQE1", 1, 1, 0);
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registerField(Fields::IQE2, "IQE2", 2, 1, 0);
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registerField(Fields::IQE3, "IQE3", 3, 1, 0);
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registerField(Fields::IQE4, "IQE4", 4, 1, 0);
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registerField(Fields::IQE5, "IQE5", 5, 1, 0);
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registerField(Fields::IQE6, "IQE6", 6, 1, 0);
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registerField(Fields::IQE7, "IQE7", 7, 1, 0);
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registerField(Fields::IQE8, "IQE8", 8, 1, 0);
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registerField(Fields::IQE9, "IQE9", 9, 1, 0);
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registerField(Fields::IQE10, "IQE10", 10, 1, 0);
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registerField(Fields::IQE11, "IQE11", 11, 1, 0);
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registerField(Fields::IQE12, "IQE12", 12, 1, 0);
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registerField(Fields::IQE13, "IQE13", 13, 1, 0);
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registerField(Fields::TCM7, "TCM7", 16, 1, 0);
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registerField(Fields::TCM8, "TCM8", 17, 1, 0);
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registerField(Fields::TCM9, "TCM9", 18, 1, 0);
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registerField(Fields::TCM10, "TCM10", 19, 1, 0);
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registerField(Fields::TCM11, "TCM11", 20, 1, 0);
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registerField(Fields::TCM12, "TCM12", 21, 1, 0);
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registerField(Fields::TCM13, "TCM13", 22, 1, 0);
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registerField(Fields::TCI7, "TCI7", 24, 1, 0);
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registerField(Fields::TCI8, "TCI8", 25, 1, 0);
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registerField(Fields::TCI9, "TCI9", 26, 1, 0);
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registerField(Fields::TCI10, "TCI10", 27, 1, 0);
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registerField(Fields::TCI11, "TCI11", 28, 1, 0);
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registerField(Fields::TCI12, "TCI12", 29, 1, 0);
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registerField(Fields::TCI13, "TCI13", 30, 1, 0);
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registerField(Fields::IQE0, "IQE0 (fromMDEC)", 0, 1, 0);
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registerField(Fields::IQE1, "IQE1 (toMDEC)", 1, 1, 0);
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registerField(Fields::IQE2, "IQE2 (SIF2/GPU)", 2, 1, 0);
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registerField(Fields::IQE3, "IQE3 (CDROM)", 3, 1, 0);
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registerField(Fields::IQE4, "IQE4 (SPU2c0)", 4, 1, 0);
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registerField(Fields::IQE5, "IQE5 (PIO)", 5, 1, 0);
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registerField(Fields::IQE6, "IQE6 (OTClear)", 6, 1, 0);
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registerField(Fields::IQE7, "IQE7 (SPU2c1)", 7, 1, 0);
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registerField(Fields::IQE8, "IQE8 (DEV9)", 8, 1, 0);
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registerField(Fields::IQE9, "IQE9 (SIF0)", 9, 1, 0);
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registerField(Fields::IQE10, "IQE10 (SIF1)", 10, 1, 0);
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registerField(Fields::IQE11, "IQE11 (fromSIO2)", 11, 1, 0);
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registerField(Fields::IQE12, "IQE12 (toSIO2)", 12, 1, 0);
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registerField(Fields::IQE13, "IQE13 (dummy)", 13, 1, 0);
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registerField(Fields::TCM7, "TCM7 (SPU2c1)", 16, 1, 0);
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registerField(Fields::TCM8, "TCM8 (DEV9)", 17, 1, 0);
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registerField(Fields::TCM9, "TCM9 (SIF0)", 18, 1, 0);
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registerField(Fields::TCM10, "TCM10 (SIF1)", 19, 1, 0);
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registerField(Fields::TCM11, "TCM11 (fromSIO2)", 20, 1, 0);
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registerField(Fields::TCM12, "TCM12 (toSIO2)", 21, 1, 0);
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registerField(Fields::TCM13, "TCM13 (dummy)", 22, 1, 0);
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registerField(Fields::TCI7, "TCI7 (SPU2c1)", 24, 1, 0);
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registerField(Fields::TCI8, "TCI8 (DEV9)", 25, 1, 0);
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registerField(Fields::TCI9, "TCI9 (SIF0)", 26, 1, 0);
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registerField(Fields::TCI10, "TCI10 (SIF1)", 27, 1, 0);
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registerField(Fields::TCI11, "TCI11 (fromSIO2)", 28, 1, 0);
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registerField(Fields::TCI12, "TCI12 (toSIO2)", 29, 1, 0);
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registerField(Fields::TCI13, "TCI13 (dummy)", 30, 1, 0);
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}
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void IOPDmacRegister_ICR1_t::writeWord(const Context_t context, const u32 value)
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@ -58,7 +58,7 @@ IOPIntcRegister_MASK_t::IOPIntcRegister_MASK_t(const char * mnemonic, const bool
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registerField(Fields::SIO1, "SIO1", 8, 1, 0);
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registerField(Fields::SPU, "SPU", 9, 1, 0);
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registerField(Fields::PIO, "PIO", 10, 1, 0);
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registerField(Fields::EVBLANK, "EVBLANK", 11, 1, 0); // End of VBLANK?
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registerField(Fields::EVBLANK, "EVBLANK", 11, 1, 0); // End of VBLANK.
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registerField(Fields::DVD, "DVD", 12, 1, 0);
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registerField(Fields::PCMCIA, "PCMCIA", 13, 1, 0);
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registerField(Fields::TMR3, "TMR3", 14, 1, 0);
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@ -7,10 +7,4 @@ SPU2Register_SPDIF_IRQINFO_t::SPU2Register_SPDIF_IRQINFO_t(const char * mnemonic
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{
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registerField(Fields::IrqCore0, "IrqCore0", 2, 1, 0);
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registerField(Fields::IrqCore1, "IrqCore1", 3, 1, 0);
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}
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bool SPU2Register_SPDIF_IRQINFO_t::isInterrupted(const Context_t context)
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{
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// Core 0 and 1 IRQ bits located at bits 2 and 3 (0xC mask).
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return ((readHword(context) & 0xC) > 0);
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}
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@ -9,7 +9,7 @@ The SPU2 SPDIF_IRQINFO register.
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Contains information about the SPU2 cores' interrupted states.
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See the SPU2-X/spu2sys.cpp file for information about the IRQ's.
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IRQ's are set, for example, when an address is accessed equaling the IRQA register pair value.
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Weird how general IRQ's not related to SPDIF use this register...
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TODO: Weird how general IRQ's not related to SPDIF use this register... Check this?
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*/
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class SPU2Register_SPDIF_IRQINFO_t : public BitfieldRegister16_t
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{
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@ -23,9 +23,4 @@ public:
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};
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SPU2Register_SPDIF_IRQINFO_t(const char * mnemonic, const bool debugReads, const bool debugWrites);
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/*
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Returns if any of the core IRQ's are set.
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*/
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bool isInterrupted(const Context_t context);
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};
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@ -57,7 +57,7 @@ int EECoreInterpreter_s::step(const Event_t & event)
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mEECoreInstruction = EECoreInstruction_t(mByteMMU->readWord(getContext(), physicalAddress));
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#if defined(BUILD_DEBUG)
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static u64 DEBUG_LOOP_BREAKPOINT = 0x10000000143138b;
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static u64 DEBUG_LOOP_BREAKPOINT = 0x100000004F94E00;
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static u32 DEBUG_PC_BREAKPOINT = 0x0;
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if (DEBUG_LOOP_COUNTER >= DEBUG_LOOP_BREAKPOINT)
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{
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@ -49,10 +49,10 @@ int SPU2_s::step(const Event_t & event)
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workDone |= handleDMATransfer();
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workDone |= handleSoundGeneration();
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}
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// Do an interrupt check, and send signal to the IOP INTC if needed.
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handleInterruptCheck();
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// Do an interrupt check, and send signal to the IOP INTC if needed.
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handleInterruptCheck();
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}
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// SPU2 has completed 1 cycle.
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#if ACCURACY_SKIP_TICKS_ON_NO_WORK
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@ -246,7 +246,7 @@ void SPU2_s::writeHwordMemory(const u32 hwordPhysicalAddress, const u16 value) c
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void SPU2_s::handleInterruptCheck() const
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{
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if (mCore->ATTR->getFieldValue(getContext(), SPU2CoreRegister_ATTR_t::Fields::IRQEnable)
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&& mSPU2->SPDIF_IRQINFO->isInterrupted(getContext()))
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&& mSPU2->SPDIF_IRQINFO->getFieldValue(getContext(), SPU2Register_SPDIF_IRQINFO_t::Fields::IRQ_KEYS[mCore->getCoreID()]))
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{
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// IRQ was set, notify the IOP INTC.
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mINTC->STAT->setFieldValue(getContext(), IOPIntcRegister_STAT_t::Fields::SPU, 1);
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