Emulation/orbum
1
0
Fork 0
mirror of https://github.com/hch12907/orbum.git synced 2024-06-02 19:38:16 -04:00
Code Issues Packages Projects Releases Wiki Activity

Commit graph

  • 7d93972e73 Switched from std::unordered_map to boost::container::flat_map... much better when run under the optimised build. From 20s run time to almost nothing! Marco Satti 2016-09-24 16:56:24 +0800
  • 0155f0df33 Change the vmMain variable in each subclass to non-const, allowing emulation to be stopped. Marco Satti 2016-09-24 13:31:33 +0800
  • 5ef9224fa6 Change EE core exception model (again) from a queue to a single state... A queue is unnecessary, I believe. Marco Satti 2016-09-23 20:38:53 +0800
  • a044e086b1 Major change to the emulator loop - added in a way to synchronise everything properly. Starting to run into performace issues with the bitfield storage object... Need to look into it, not sure why. Marco Satti 2016-09-23 16:22:54 +0800
  • ad97523489 Moved COP1.ACC initialisation from header to unit file... not sure why this compiled before..? Marco Satti 2016-09-20 17:21:39 +0800
  • 2629c6dd45 Rename COP0 and COP1 bitfield registers to have COPx infront. Currently reading through the DMAC documentation. Marco Satti 2016-09-20 17:14:39 +0800
  • 21bdb7171e Added in the EE timers functionality. One thing I have figured out that wasnt clear before - a 'clock' from a crystal is regarded as an 'event' in programming, and a 'signal' is an 'environment variable'. Marco Satti 2016-09-19 17:03:36 +0800
  • 40b6fa48f9 I think I finally figured out how the timers should work.. Based of the old PCSX2 method of using the ee core instruction cycles for busclk. Still unsure of how h-blnk will work, and gate logic. Also added preperation for specific EE registers. Marco Satti 2016-09-15 22:31:10 +0800
  • c69de6564c Rename the current TimerHandler to EECoreTimerHandler so to not confuse between the EECore.COP0.Count/Compare and the 4 x EE Timer's Marco Satti 2016-09-14 18:19:49 +0800
  • b870cb136a Forgot to check the COP0.Status IM2 bit before sending the exception to be processed. Also, having a hard time figuring out how to implement the external timers.. Marco Satti 2016-09-11 21:31:44 +0800
  • 5f7b1cf64c Framework for the EE (DMAC, INTC, etc) put into place. Marco Satti 2016-09-11 02:17:49 +0800
  • 88e004937b Change the Int exception info type flag names to reflect the signal's, not the EE Core register names. Marco Satti 2016-09-10 22:18:10 +0800
  • 2405b67ba0 Implemented properly all of the EE registers, VU memories and GS privileged registers as defined on page 21 - 26. Moved a few definitions around to better reflect the structure and scope of them. Marco Satti 2016-09-10 14:34:13 +0800
  • fd543e0e83 Begin work on implementing the EE registers, and some cleanup effort (especially with regards to how logging works). Marco Satti 2016-09-05 19:15:39 +0800
  • 3c28e1dca1 Change the bitfield register map key from std::string to const char *, as its becoming more of a performance bottleneck. Marco Satti 2016-09-05 00:00:26 +0800
  • 4241ce7330 Cleaned up the SIO_TXFIFO message functionality to use std::string. Marco Satti 2016-09-04 22:36:31 +0800
  • a468eecbc9 Oh god that was an embarrasing mistake.. Used logical OR instead of bitwise OR in calculating PS2 physical addresses. Spent a while tracking this down... Marco Satti 2016-09-03 20:31:25 +0800
  • 751f90c5e0 Made a mistake in initalising objects... Marco Satti 2016-09-02 20:45:55 +0800
  • 6a98fbd0e9 Reworked the includes - compile times were getting long so tried to use forward declarations where possible and only use headers for declarations. Marco Satti 2016-09-02 15:21:25 +0800
  • 2c12d62bd5 Almost finished with the MCH EE register region... Too tired to continue :(. Marco Satti 2016-09-01 22:56:58 +0800
  • 130893cb02 Start adding in proper EE registers, such as the SIO etc. Custom functionality is able to be done (thanks to the VM MMU rework in the last couple of commits), so that special registers (*undocumented*... thanks Sony) can be implemented without much spaghetti code. Marco Satti 2016-09-01 22:04:38 +0800
  • 26ab25b49f Fixed up the MULT/MULTU instructions (oops), BIOS now gets to reading 0x1000f440 but reads the wrong value - need to implement this EE register properly. Something to do with MCH_RICM/DRD but pcsx2 says information lacking... Marco Satti 2016-09-01 16:29:11 +0800
  • 89821599bc Reworked the VM MMU slightly, to operate based on read/write functions (and by extension, "storage objects"), which allows for regions of the PS2's physical memory to act in special ways - for example, the EE register 'reserved' regions, where writes are now disregarded and reads return 0. Marco Satti 2016-09-01 00:55:08 +0800
  • 58659dc366 Implemented EE Core cycle counting and COP0.Count/COP0.Compare updating/interrupt. BIOS progresses until it tries to do something with 0x1000F430, which I can't find any description of, but its in the EE register region. Marco Satti 2016-08-30 23:31:01 +0800
  • 2f8f2f193a Fixed up many instruction errors - BIOS now loads correctly until it starts checking the timers - which havent been fully implemented yet! Took me almost 3 hours to fix up the ANDI instruction bug, which gives you an idea of how hard it is to find them :). Marco Satti 2016-08-30 15:24:18 +0800
  • 19e390d5cb Very happy! Got the scratchpad ram to work through the TLB/PS2 MMU. The documentation was a little confusing so glad to get it working. Next problem: When an exception handler resumes, it is at the wrong PC (+4 more than it should be). Marco Satti 2016-08-29 18:00:01 +0800
  • 11e1885409 Forgot to return early when an exception is raised - added in return statements. Marco Satti 2016-08-28 14:07:47 +0800
  • 14291c8bd3 Almost got the TLB working properly - something wrong with the first tlb entry the bios writes... Need to investigate it. Marco Satti 2016-08-28 12:32:06 +0800
  • 72146199c1 Finished the exceptions rewrite, which can make it thread safe. Marco Satti 2016-08-27 02:12:23 +0800
  • 179cd2df47 The exception model currently in place is not going to work in a threaded setting - need to rework it. From looking at the PCSX2 source code, they check if any exceptions have been raised after each jump-type instruction (polling system). Changes are in progress to reflect a polling method. Also added in specific exception functionality, including external exception parameters needed. Marco Satti 2016-08-25 00:17:45 +0800
  • 06b899ac48 Preping EE register implementations (starting to work on the contents in EE Users Manual). Marco Satti 2016-08-23 17:21:25 +0800
  • 9fd8ebc93b Fixed up the kernel mode detection (thanks to gregory @ pcsx2), fixed up the ORI instruction. Stops execution on accessing the EE registers, which is where it should stop for now. Marco Satti 2016-08-21 23:34:31 +0800
  • 8a8a018057 Milestone commit! Can now launch the EECore interpreter, and start emulation. There are a few remaining intstructions to implement (TLB* being the more important ones), and the interpreter also doesnt get far before a runtime_error is raised... but it is progress :). Marco Satti 2016-08-21 12:13:00 +0800
  • 7aa8e266ae All remaining EECore instructions completed, just need to determine how to set PC for each instruction and figure out branch delays etc. Marco Satti 2016-08-19 00:38:05 +0800
  • 7dd81de250 Added in Special data transfer instructions, and checking for cop0 usability before operating on the registers. Marco Satti 2016-08-18 15:54:02 +0800
  • 76c787f999 Store mem instructions done. Marco Satti 2016-08-17 23:24:35 +0800
  • f591c8c38e Finished Load instructions. Marco Satti 2016-08-17 13:32:39 +0800
  • bc1c3d13e4 Forgot to add in my FPU notes I made a while back. Marco Satti 2016-08-15 18:34:46 +0800
  • 054a216a61 Trialing another method of throwing exceptions - for example, within the COP1 registers, they now check that COP1 is available before commiting a read or write. Marco Satti 2016-08-15 18:02:04 +0800
  • 72edb8355b Re-organisation in preparation for the load to memory instructions... I hope I have it right this time. All of the EECore instruction implmentations have been changed to member functions as the memory instructions rely on the MMU, which is easily accessed through the InterpreterEECore class. Marco Satti 2016-08-15 01:45:59 +0800
  • 53e055e55c Done Reg transfer instructions. Marco Satti 2016-08-14 01:20:03 +0800
  • f9c9ed0da3 Fix VS filters. Marco Satti 2016-08-13 15:46:10 +0800
  • 7d393a76ad Finished Others instructions. 4 pages to go. Marco Satti 2016-08-13 15:02:24 +0800
  • ec3f5e0a36 Implemented Reordering instructions. Renamed EECoreFPUUtil to EECoreCOP1Util so there is no confusion (I said before that I would try to use COPx consistently instead of eg FPU). Marco Satti 2016-08-13 13:46:37 +0800
  • 733afd34be DFC and min/max and compare done... 5 pages to go :). Marco Satti 2016-08-13 00:24:16 +0800
  • 737e420ef6 Finished logical implementations. Marco Satti 2016-08-12 22:42:45 +0800
  • d735059e0f Started Logical instructions. Marco Satti 2016-08-12 19:59:01 +0800
  • 68f430e824 Shift instructions done. Marco Satti 2016-08-12 19:49:22 +0800
  • cdbbc406c0 Fix VS filter hierarchy. Marco Satti 2016-08-12 14:20:18 +0800
  • 70bbb472f4 Finished float arithmetic instructions. Next is shift instructions. Marco Satti 2016-08-12 13:25:26 +0800
  • aeef21a1f5 Unfortunately the FPR functionality talked about in last commit cant happen - unless the instruction context is parsed to the write, there is no way to determine which flags to set... so it basically becomes useless. It still helps for ZeroRegister128_t and PCRegister32_t, so I will keep it for now. Began work on EECoreFPUUtil is a new static class for helping with the FPU instructions. Marco Satti 2016-08-12 11:37:56 +0800
  • f324ab2678 Major rework of how registers are implemented - I am testing this way after looking at the FPU source code. By making subclassed objects with overriden read/write B/H/W/D functions, we can customise how values are written. For example, any writes to the ZeroRegister128_t are now discarded. If the old way was still used, then you would need to repeat the checks, for example on FPR writes, in each instruction - this way it is all done through the FPRRegister32_t class. The downside of this is that it makes the code a bit harder to read, and there may be a (small) performance impact. Marco Satti 2016-08-11 00:00:25 +0800
  • d9d0fa0fa9 Started float instructions. Marco Satti 2016-08-09 11:26:09 +0800
  • da8039fbf6 Finished Mult-Add instructions. Marco Satti 2016-08-08 16:31:44 +0800
  • 9280345618 Started implementing integer mult-add instructions. Marco Satti 2016-08-07 23:29:25 +0800
  • f2e55aa094 Implemented Mult/Div instructions. Marco Satti 2016-08-07 12:50:48 +0800
  • ca81ad3584 Begin Mult/Div implementation. Marco Satti 2016-08-07 10:46:40 +0800
  • f31b234b4c Implemented all of the Integer Add/Sub instructions. (1/9 pages completed). Marco Satti 2016-08-06 18:54:02 +0800
  • 30a560a96e Started implementations of R5900 instructions! :) Marco Satti 2016-08-05 23:00:17 +0800
  • 17b91a34f8 Added a consolidated master list to the R5900 Impl. register (created macro to do this)... Needed it for printing! Forgot to add in the instruction as a parameter to the impl. functions.. Fixed. Marco Satti 2016-08-05 21:15:02 +0800
  • 2879bc3833 A bit more structural work in preperation for all of the R5900 instruction implementations. Marco Satti 2016-08-05 16:16:55 +0800
  • 774d50599c Finished adding in all of the R5900 instruction declarations from the EE Core Instruction Manual, starting to work on implementing them in the interpreter. Marco Satti 2016-08-05 13:17:10 +0800
  • f452a6a4e2 Assigned all opcodes implementation index numbers, in total there are 258. Marco Satti 2016-08-03 22:01:19 +0800
  • ec88152ca4 Started on a implementation register, as there is quite a lot of instructions to implement. The primary function of this file is to provide an index number which can be used in a lookup table (I am not a fan of static function pointers, which is how old PCSX2 is currently working). Marco Satti 2016-08-03 20:54:47 +0800
  • bb0c1817f8 Implemented Boot ROM region & initalisation of it. Marco Satti 2016-08-02 23:20:05 +0800
  • 8cc8a19046 Implemented PS2's MMU/TLB. Still need to finish up the scratchpad/cache access but the bulk of it is done. Marco Satti 2016-08-01 23:37:00 +0800
  • 900246d7f8 Implemented exception handler. I haven't considered how the recompiler may interface with this (there is too much to think about at this time) so it is subject to change. Marco Satti 2016-07-29 22:31:02 +0800
  • 073d9d5ab2 Implemented the branch delay slot as a state feature of the R5900... Have not dealt with this before, so a bit of trial and error. Marco Satti 2016-07-29 20:19:50 +0800
  • bb07264ac8 A couple of misc/organisational changes. Marco Satti 2016-07-28 23:06:58 +0800
  • 1206233d76 Reorganised directory structure - it will eventually be a large project that needs to be well organised from the beginning. Marco Satti 2016-07-28 20:35:05 +0800
  • 04ee4f3320 Started implementing the FPU. Marco Satti 2016-07-27 18:44:49 +0800
  • 4e943cf87d Reworked implementation of MMU - all tests pass now and it reads much better. Marco Satti 2016-07-26 18:10:04 +0800
  • 22c7c90271 Heavily worked on the VM MMU again - reading into the docs, the EE memory map needs to be aligned with 16 byte boundaries - which means the page table minimum unit must be 16B... Re did it as a 2-level page table (4MB and 16B), still a few issues to sort out. Also worked on the exception handler and related components. Marco Satti 2016-07-25 23:51:32 +0800
  • f19524675c Added in a couple of tests for the instruction type - seems to work well. Marco Satti 2016-07-22 23:23:00 +0800
  • 4d6c3124ba Forgot to add the unit test library as a git submodule. Fixed. Marco Satti 2016-07-22 18:33:47 +0800
  • c727b550dd Restructured whole project a little and added in unit testing (through GoogleTest). Marco Satti 2016-07-22 17:33:16 +0800
  • 8254e89d49 Added in the VM MMU component, responsible for translating PS2 physical addresses into client virtual addresses (done via page table). Fixed up some wording and syntax. Marco Satti 2016-07-22 14:39:49 +0800
  • d0baecf060 Started work on the R5900 interpreter and the MMU unit. Its likely that I will get the MMU wrong at first as it is something completely new to me. Marco Satti 2016-07-17 13:59:23 +0800
  • dc1a608598 Reworked the Instruction_t class to provide functionality for R, J and I types, as you are not allowed to cast from a parent class to child class. Marco Satti 2016-07-15 13:05:53 +0800
  • a0ed003c52 Changes to the structure of the emulator. Created the VMMain & components that will be used for control of the core emulation (component programming model). I believe this programming pattern is used also eg: in game engines. Marco Satti 2016-07-14 21:59:06 +0800
  • a287e01c85 Added in all of the COP0 registers, using the new BitfieldRegister_t class. Marco Satti 2016-07-10 13:42:01 +0800
  • 168bd6e360 Added more COP0 registers in, but about to change the way they are implemented as it is too tedious to write out each time. Marco Satti 2016-07-09 15:01:44 +0800
  • a42243855b Add more COP0 registers, update readme for markdown syntax. Marco Satti 2016-07-08 09:58:31 +0800
  • 0c3058b349 Added in the get/set bit range (ie: bitfields) functions into Register32_t, which will be used a lot upcoming. Also note I will focus on getting the core implemention ready, then optimise later. Started work on implementing COP0 registers. Marco Satti 2016-07-07 22:59:24 +0800
  • 93de3d9269 Fixed up namespaces. Apparently VS doesnt like macros for namespaces so I have limited the nesting to 2 namespaces in order to increase visibility. Marco Satti 2016-07-06 22:10:04 +0800
  • bd1c91942a First commit. Implemented parts of the EE core. Marco Satti 2016-07-06 20:56:06 +0800
  • 12d66128a2 Add project files. Marco Satti 2016-07-06 12:07:56 +0800
  • 5787a5b272 Add .gitignore and .gitattributes. Marco Satti 2016-07-06 12:07:55 +0800