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56 lines
1.9 KiB
C++
56 lines
1.9 KiB
C++
#pragma once
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#include <cereal/cereal.hpp>
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#include "Common/Constants.hpp"
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#include "Common/Types/Mips/BranchDelaySlot.hpp"
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#include "Common/Types/Register/PcRegisters.hpp"
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#include "Common/Types/Register/SizedQwordRegister.hpp"
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#include "Common/Types/Register/SizedWordRegister.hpp"
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/// The R5900 is the EE Core's CPU.
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/// It has been modified from a stock R5900 to include Sony specific instructions
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/// (multimedia instructions targeting 128-bit operations etc).
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/// Uses a little-endian configuration.
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class EeCoreR5900
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{
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public:
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EeCoreR5900();
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/// The 32-bit Program Counter (PC) register. See EE Core Users manual, pg 61.
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/// Points to the current instruction virtual address.
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WordPcRegister pc;
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/// Branch delay slot holding area.
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BranchDelaySlot<> bdelay;
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/// The R5900 general purpose registers (GPR's) are 128-bit long.
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/// The upper 64-bits are only used when specific instructions are run, such as
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/// using the EE Core specific multimedia instructions (parallel instructions). Example: PADDB.
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/// See EE Core Users Manual, pg 60.
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SizedQwordRegister gpr[Constants::EE::EECore::R5900::NUMBER_GP_REGISTERS];
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/// The HI and LO registers. See EE Core Users manual, pg 60.
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/// These registers are used to hold the results of integer multiply and divide operations.
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SizedQwordRegister hi;
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SizedQwordRegister lo;
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/// The Shift Amount (SA) register. See EE Core Users manual, pg 61.
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/// The SA register is used for holding funnel shift instruction results.
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/// See the EE Core instruction QFSRV for more details (SA is only used for this instruction).
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SizedWordRegister sa;
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public:
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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CEREAL_NVP(pc),
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CEREAL_NVP(bdelay),
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CEREAL_NVP(gpr),
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CEREAL_NVP(hi),
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CEREAL_NVP(lo),
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CEREAL_NVP(sa)
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);
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}
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}; |