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135 lines
4.2 KiB
C++
135 lines
4.2 KiB
C++
#pragma once
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#include <cereal/cereal.hpp>
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#include <cereal/types/polymorphic.hpp>
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#include "Common/Types/Mips/MipsCoprocessor0.hpp"
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#include "Common/Types/Register/SizedWordRegister.hpp"
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/// IOP Core COP0 registers.
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/// See here where you can find more information: http://hitmen.c02.at/files/docs/psx/psx.pdf (thanks to Joshua Walker).
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/// Context register of the IOP COP0.
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class IopCoreCop0Register_Context : public SizedWordRegister
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{
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public:
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static constexpr Bitfield BADVPN2 = Bitfield(2, 19);
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static constexpr Bitfield PTEBASE = Bitfield(21, 11);
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};
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/// Status register of the IOP COP0.
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class IopCoreCop0Register_Status : public SizedWordRegister
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{
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public:
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static constexpr Bitfield IEC = Bitfield(0, 1);
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static constexpr Bitfield KUC = Bitfield(1, 1);
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static constexpr Bitfield IEP = Bitfield(2, 1);
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static constexpr Bitfield KUP = Bitfield(3, 1);
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static constexpr Bitfield IEO = Bitfield(4, 1);
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static constexpr Bitfield KUO = Bitfield(5, 1);
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static constexpr Bitfield IM = Bitfield(8, 8);
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static constexpr Bitfield ISC = Bitfield(16, 1);
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static constexpr Bitfield SWC = Bitfield(17, 1);
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static constexpr Bitfield PZ = Bitfield(18, 1);
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static constexpr Bitfield CM = Bitfield(19, 1);
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static constexpr Bitfield PE = Bitfield(20, 1);
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static constexpr Bitfield TS = Bitfield(21, 1);
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static constexpr Bitfield BEV = Bitfield(22, 1);
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static constexpr Bitfield RE = Bitfield(25, 1);
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static constexpr Bitfield CU = Bitfield(28, 4);
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static constexpr uword INITIAL_VALUE = 0x00400000;
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IopCoreCop0Register_Status();
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/// Pushes/Pops the IE & KU bits (used in exception handling) to an older or earlier level (similar to a stack).
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/// In the bitfield names for those bits,
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/// "c" refers to the current status.
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/// "p" refers to the previous status.
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/// "o" refers to the oldest status.
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/// When pushing, clears the expunged bits to 0 (poping contains old values).
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void push_exception_stack();
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void pop_exception_stack();
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/// Upon writes:
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/// - Caches the operating context for COP0.
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/// - Caches the interrupt masked state for the CPU.
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void write_uword(const uword value) override;
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/// Current cached CPU interrupts masked state.
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bool interrupts_masked;
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/// Current cached COP0 operating context state.
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MipsCoprocessor0::OperatingContext operating_context;
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private:
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/// Updates the cached interrupt masked state.
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/// Does so by checking the master ERL, EXL, EIE and IE bit.
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void handle_interrupts_masked_update();
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/// Updates the operation context state.
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/// Uses the KSU, ERL and EXL bits.
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void handle_operating_context_update();
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public:
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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cereal::base_class<SizedWordRegister>(this),
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CEREAL_NVP(interrupts_masked),
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CEREAL_NVP(operating_context)
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);
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}
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};
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/// Cause register of the IOP COP0.
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class IopCoreCop0Register_Cause : public SizedWordRegister
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{
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public:
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static constexpr Bitfield EXCCODE = Bitfield(2, 5);
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static constexpr Bitfield IP = Bitfield(8, 8);
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static constexpr Bitfield CE = Bitfield(28, 2);
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static constexpr Bitfield BD = Bitfield(31, 1);
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IopCoreCop0Register_Cause();
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/// Clears all of the IRQ lines.
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void clear_all_irq();
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/// Sets the given IRQ line.
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void set_irq_line(const int irq);
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/// Clears the given IRQ line.
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void clear_irq_line(const int irq);
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/// Syncs the register state with the IRQ flags and returns the register value.
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uword read_uword() override;
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private:
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/// IRQ line flags.
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bool irq_lines[8];
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public:
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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cereal::base_class<SizedWordRegister>(this),
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CEREAL_NVP(irq_lines)
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);
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}
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};
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/// The PRId register of the IOP COP0.
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/// Some different initial values to EE Core implementation, same structure.
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class IopCoreCop0Register_Prid : public SizedWordRegister
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{
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public:
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static constexpr Bitfield REV = Bitfield(0, 8);
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static constexpr Bitfield IMP = Bitfield(8, 8);
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static constexpr uword INITIAL_VALUE = 0x1F;
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IopCoreCop0Register_Prid();
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}; |