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83 lines
3.7 KiB
C++
83 lines
3.7 KiB
C++
#pragma once
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#include <cereal/cereal.hpp>
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#include "Common/Types/Bitfield.hpp"
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#include "Common/Types/FifoQueue/DmaFifoQueue.hpp"
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#include "Common/Types/Register/ByteRegister.hpp"
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#include "Common/Types/Register/SizedHwordRegister.hpp"
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#include "Common/Types/ScopeLock.hpp"
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/// SIO0 ctrl register.
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/// Needs to be accessed atomically by the SIO0 and SIO2 within emulator.
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/// Assumed to be similar to the PSX SIO (pad/mc), consult no$psx docs.
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class Sio0Register_Ctrl : public SizedHwordRegister, public ScopeLock
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{
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public:
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static constexpr Bitfield TXEN = Bitfield(0, 1); // Enable SIO0 transmit.
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static constexpr Bitfield DTR = Bitfield(1, 1); // (Data terminal ready) SIO is ready to receive data from pad/mc selected by PORT.
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static constexpr Bitfield RXEN = Bitfield(2, 1); // 0 means normal operation, RXEN is always enabled otherwise? (not sure what 1: "force" means)
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static constexpr Bitfield RESET_IRQ = Bitfield(4, 1); // This is like a "master controller has acknowledged IRQ" bit, don't be confused with SIO_RESET.
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static constexpr Bitfield SIO_RESET = Bitfield(6, 1); // This is like a global SIO reset (see no$psx docs).
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static constexpr Bitfield RX_INT_MODE = Bitfield(8, 2); // Receive buffer interrupt mode, used with bit 11.
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static constexpr Bitfield TX_INT_EN = Bitfield(10, 1); // Transmit interrupt enable.
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static constexpr Bitfield RX_INT_EN = Bitfield(11, 1); // receive interrupt enable, interrupt when RX_INT_MODE bytes have been received.
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static constexpr Bitfield ACK_INT_EN = Bitfield(12, 1); // Pad/mc acknowledge line interrupt enable (used with STAT.DSR).
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static constexpr Bitfield PORT = Bitfield(13, 1); // Currently selected port (0/1).
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/// Scope locked bus writes.
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void byte_bus_write_uhword(const BusContext context, const usize offset, const uhword value) override;
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};
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/// SIO0 stat register.
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/// Needs to be accessed atomically by the SIO0 and SIO2 within emulator.
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/// Assumed to be similar to the PSX SIO (pad/mc), consult no$psx docs.
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class Sio0Register_Stat : public SizedHwordRegister, public ScopeLock
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{
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public:
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static constexpr Bitfield TX_RDY1 = Bitfield(0, 1);
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static constexpr Bitfield RX_NONEMPTY = Bitfield(1, 1); // RX FIFO non-empty.
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static constexpr Bitfield TX_RDY2 = Bitfield(2, 1);
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static constexpr Bitfield PARITY_ERR = Bitfield(3, 1);
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static constexpr Bitfield DSR = Bitfield(7, 1); // (Data set ready) Acknowledge input line level by pad/mc.
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static constexpr Bitfield IRQ = Bitfield(9, 1); // IRQ line, setting this causes an interrupt to fire.
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/// Scope locked bus writes.
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void byte_bus_write_uhword(const BusContext context, const usize offset, const uhword value) override;
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};
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/// SIO0 data "register".
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/// This is a hybrid FIFO port, where writing and reading access 2 different
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/// FIFO queues. Tx direction means from SIO2 to SIO0, Rx direction means from
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/// SIO0 to SIO2.
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class Sio0Register_Data : public ByteRegister
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{
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public:
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Sio0Register_Data();
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void initialize() override;
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ubyte read_ubyte() override;
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void write_ubyte(const ubyte value) override;
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/// FIFO queues.
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/// These queues are meant to be accessed directly from the SIO0 only, for
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/// all other components, this is meant to be accessed as a register.
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DmaFifoQueue<> command_queue;
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DmaFifoQueue<> response_queue;
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/// Reference to the SIO0 stat register, needed to change status bits
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/// depending on the different FIFO queue states (tx full/rx empty).
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Sio0Register_Stat* stat;
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public:
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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CEREAL_NVP(command_queue),
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CEREAL_NVP(response_queue)
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);
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}
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};
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