mirror of
https://github.com/hch12907/orbum.git
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252 lines
8.2 KiB
C++
252 lines
8.2 KiB
C++
#include <boost/format.hpp>
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#include "Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter.hpp"
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#include "Core.hpp"
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#include "Resources/Ee/Vpu/Vu/VuUnits.hpp"
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// All instructions here are related to registers.
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// Particularly load/store
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void CVuInterpreter::MOVE(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedQwordRegister& reg_source = unit->vf[inst.fs()];
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SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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reg_dest.write_uword(reg_source.read_uword(field), field);
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}
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}
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}
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void CVuInterpreter::MFIR(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedHwordRegister& reg_source = unit->vi[inst.is()];
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SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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reg_dest.write_uword(reg_source.read_uhword(), field);
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}
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}
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}
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void CVuInterpreter::MTIR(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedQwordRegister& reg_source = unit->vf[inst.fs()];
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SizedHwordRegister& reg_dest = unit->vi[inst.it()];
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reg_dest.write_uhword(reg_source.read_uword(inst.fsf()) & 0xFFFF);
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}
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void CVuInterpreter::MR32(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedQwordRegister& reg_source = unit->vf[inst.fs()];
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SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
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reg_dest.write_uword(reg_source.read_uword(VuVectorField::W), VuVectorField::X);
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reg_dest.write_uword(reg_source.read_uword(VuVectorField::X), VuVectorField::Y);
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reg_dest.write_uword(reg_source.read_uword(VuVectorField::Y), VuVectorField::Z);
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reg_dest.write_uword(reg_source.read_uword(VuVectorField::Z), VuVectorField::W);
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}
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void CVuInterpreter::LQ(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedHwordRegister& reg_source = unit->vi[inst.is()];
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SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
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const uword address = (inst.imm11() + reg_source.read_uhword()) * NUMBER_BYTES_IN_QWORD;
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const uqword source = unit->bus.read_uqword(BusContext::Vu, address);
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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// Investigate?: Endianness scares me
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reg_dest.write_float(source.uw[field], field);
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}
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}
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}
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void CVuInterpreter::LQD(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedHwordRegister& reg_source = unit->vi[inst.is()];
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SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
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// Pre-decrement VI first
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reg_source.write_uhword(reg_source.read_uhword() - 1);
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const uword address = reg_source.read_uhword() * NUMBER_BYTES_IN_QWORD;
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const uqword source = unit->bus.read_uqword(BusContext::Vu, address);
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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// Investigate?: Endianness scares me
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reg_dest.write_float(source.uw[field], field);
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}
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}
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}
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void CVuInterpreter::LQI(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedHwordRegister& reg_source = unit->vi[inst.is()];
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SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
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const uword address = reg_source.read_uhword() * NUMBER_BYTES_IN_QWORD;
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const uqword source = unit->bus.read_uqword(BusContext::Vu, address);
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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// Investigate?: Endianness scares me
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reg_dest.write_float(source.uw[field], field);
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}
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}
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// Post-increment the VI
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reg_source.write_uhword(reg_source.read_uhword() + 1);
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}
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void CVuInterpreter::SQ(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedQwordRegister& reg_source_1 = unit->vf[inst.fs()];
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SizedHwordRegister& reg_source_2 = unit->vi[inst.it()];
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const uword address = (inst.imm11() + reg_source_2.read_uhword()) * NUMBER_BYTES_IN_QWORD;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
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}
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}
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}
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void CVuInterpreter::SQD(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedQwordRegister& reg_source_1 = unit->vf[inst.fs()];
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SizedHwordRegister& reg_source_2 = unit->vi[inst.it()];
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reg_source_2.write_uhword(reg_source_2.read_uhword() - 1);
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const uword address = reg_source_2.read_uhword() * NUMBER_BYTES_IN_QWORD;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
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}
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}
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}
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void CVuInterpreter::SQI(VuUnit_Base* unit, const VuInstruction inst)
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{
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// MEM(Ft) = Fs
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SizedQwordRegister& reg_source_1 = unit->vf[inst.fs()];
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SizedHwordRegister& reg_source_2 = unit->vi[inst.ft()]; // Mem Addr.
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// Real address obtained by VI * 16 (qword addressing).
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const uword address = reg_source_2.read_uhword() * NUMBER_BYTES_IN_QWORD;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
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}
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}
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// Post increment.
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reg_source_2.write_uhword(reg_source_2.read_uhword() + 1);
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}
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void CVuInterpreter::ILW(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedHwordRegister& reg_source = unit->vi[inst.is()];
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SizedHwordRegister& reg_dest = unit->vi[inst.it()];
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const uword address = (inst.imm15() + reg_source.read_uhword()) * NUMBER_BYTES_IN_QWORD;
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const uword source = unit->bus.read_uqword(BusContext::Vu, address).uw[inst.dest()];
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reg_dest.write_uhword(static_cast<uhword>(source));
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}
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void CVuInterpreter::ISW(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedHwordRegister& reg_source_1 = unit->vi[inst.it()];
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SizedHwordRegister& reg_source_2 = unit->vi[inst.is()];
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const uword address = (inst.imm15() + reg_source_2.read_uhword()) * NUMBER_BYTES_IN_QWORD;
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uhword());
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}
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}
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}
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void CVuInterpreter::ILWR(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedHwordRegister& reg_source = unit->vi[inst.is()];
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SizedHwordRegister& reg_dest = unit->vi[inst.it()];
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const uword address = reg_source.read_uhword() * NUMBER_BYTES_IN_QWORD;
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const uword source = unit->bus.read_uqword(BusContext::Vu, address).uw[inst.dest()];
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reg_dest.write_uhword(static_cast<uhword>(source));
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}
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void CVuInterpreter::ISWR(VuUnit_Base* unit, const VuInstruction inst)
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{
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// MEM(Fs) = Ft.
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SizedHwordRegister& reg_source_1 = unit->vi[inst.it()]; // Data.
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SizedHwordRegister& reg_source_2 = unit->vi[inst.is()]; // Mem Addr.
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// Real address obtained by VI * 16.
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const uword address = reg_source_2.read_uhword() * NUMBER_BYTES_IN_QWORD;
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// 32-bit write for each dest subfield. Upper 16-bits of VI[Ft] value is set to 0.
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uhword());
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}
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}
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}
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void CVuInterpreter::LOI(VuUnit_Base* unit, const VuInstruction inst)
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{
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// Call this instruction when the I bit of the upper instruction is set
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// And pass the lower instruction in
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unit->i.write_uword(inst.value);
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// (In case you are wondering... LOI is a pseudo-instruction, it's
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// not supposed to be referenced)
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}
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void CVuInterpreter::MFP(VuUnit_Base* unit, const VuInstruction inst)
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{
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SizedWordRegister& reg_source = unit->p;
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SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
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for (auto field : VuVectorField::VECTOR_FIELDS)
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{
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if (inst.test_dest_field(field))
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{
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reg_dest.write_uword(reg_source.read_uword(), field);
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}
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}
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}
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