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51 lines
1.6 KiB
C++
51 lines
1.6 KiB
C++
#pragma once
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#include "Common/Constants.hpp"
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#include "Common/Types/Mips/MipsCoprocessor.hpp"
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#include "Common/Types/Register/SizedWordRegister.hpp"
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#include "Resources/Ee/Core/EeCoreCop0.hpp"
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#include "Resources/Ee/Core/EeCoreFpuRegisters.hpp"
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/// FPU refers to the FPU (floating-point unit) coprocessor, attached as COP1.
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/// See EE Core Users Manual, chapter 8.
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class EeCoreFpu : public MipsCoprocessor
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{
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public:
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EeCoreFpu();
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/// Checks if the FPU coprocessor (FPU) is usable, by looking at the COP0 CU[1] bit.
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/// CU[1] > 0 means FPU is usable.
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bool is_usable() override;
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/// 32 general purpose registers, called FPR's.
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/// See EE Core Users Manual, page 157.
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SizedWordRegister fpr[Constants::EE::EECore::FPU::NUMBER_REGISTERS];
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/// Accumulator register, used for multiply-accumulate type instructions.
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/// See EE Core Users Manual, page 157.
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SizedWordRegister acc;
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/// FPU defines 2 control registers, which are implemented as bitfield registers.
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/// See EE Core Users Manual, page 158.
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EeCoreFpuRegister_Irr irr;
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EeCoreFpuRegister_Csr csr;
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/// Array of control registers.
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/// Only FCR[0] and [31] are defined.
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SizedWordRegister* fcr[Constants::EE::EECore::FPU::NUMBER_REGISTERS];
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/// Pointer to the EE Core COP0 coprocessor, needed for the Status register.
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EeCoreCop0* cop0;
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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CEREAL_NVP(fpr),
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CEREAL_NVP(acc),
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CEREAL_NVP(irr),
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CEREAL_NVP(csr)
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);
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}
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};
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