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105 lines
2.6 KiB
C++
105 lines
2.6 KiB
C++
#pragma once
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/// Custom Mask type, provides useful cached values when constructed.
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struct Mask
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{
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Mask(const uword pagemask = 0) :
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pagemask(pagemask),
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evenodd_mask(1 << 12),
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tlb_mask(0xFFFFE000)
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{
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// Determine evenodd index.
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// Values have been precalculated.
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switch (pagemask & 0xFFF)
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{
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case 0x0: // 4KB
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evenodd_mask = (1 << 12);
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break;
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case 0x3: // 16 KB
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evenodd_mask = (1 << 14);
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break;
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case 0xF: // 64 KB
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evenodd_mask = (1 << 16);
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break;
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case 0x3F: // 256 KB
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evenodd_mask = (1 << 18);
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break;
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case 0xFF: // 1 MB
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evenodd_mask = (1 << 20);
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break;
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case 0x3FF: // 4 MB
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evenodd_mask = (1 << 22);
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break;
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case 0xFFF: // 16 MB
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evenodd_mask = (1 << 24);
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break;
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default:
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throw std::runtime_error("Invalid mask supplied to TLB entry");
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}
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// Calculate mask for use in TLB.
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tlb_mask = 0xFE000000 | (((~pagemask) & 0xFFF) << 13);
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}
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uword pagemask;
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uword evenodd_mask;
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uword tlb_mask;
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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CEREAL_NVP(pagemask),
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CEREAL_NVP(evenodd_mask),
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CEREAL_NVP(tlb_mask)
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);
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}
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};
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/// EE Core TLB entry, similar to a MIPS TLB entry.
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/// A TLB entry is heavily related to the COP0 registers
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/// Entry{Hi, Lo0, Lo1}, PageMask and others.
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/// See EE Core Users Manual page 120 - 123 about the TLB.
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/// For the internal struct array below, index 0 corresponds to the Even
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/// infomation, and index 1 correponds to the Odd information.
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struct EeCoreTlbEntry
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{
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Mask mask;
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uword vpn2;
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bool g;
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ubyte asid;
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bool s;
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struct
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{
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uword pfn;
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bool c;
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bool d;
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bool v;
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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CEREAL_NVP(pfn),
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CEREAL_NVP(c),
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CEREAL_NVP(d),
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CEREAL_NVP(v)
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);
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}
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} physical_info[2]; // Index 0 = Even, index 1 = Odd.
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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CEREAL_NVP(mask),
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CEREAL_NVP(vpn2),
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CEREAL_NVP(g),
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CEREAL_NVP(asid),
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CEREAL_NVP(s),
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CEREAL_NVP(physical_info[0]),
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CEREAL_NVP(physical_info[1])
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);
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}
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}; |