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69 lines
2.5 KiB
C++
69 lines
2.5 KiB
C++
#pragma once
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#include "Common/Constants.hpp"
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#include "Common/Types/Mips/MipsCoprocessor0.hpp"
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#include "Common/Types/Register/SizedWordRegister.hpp"
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#include "Resources/Iop/Core/IopCoreCop0Registers.hpp"
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using OperatingContext = MipsCoprocessor0::OperatingContext;
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/// COP0 refers to the system control coprocessor (used for manipulating the memory management and exception handling facilities of the processor, etc).
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class IopCoreCop0 : public MipsCoprocessor0
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{
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public:
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IopCoreCop0();
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/// Checks if the IOP COP0 coprocessor is usable.
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/// Can be used by the component calling this to raise a IopCoreException(coprocessor unusable) if not available.
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bool is_usable() override;
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/// Determine the CPU context. Uses the Status register.
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OperatingContext operating_context() override;
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/// IOP COP0 register implementations.
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SizedWordRegister indx; // r0: INDX.
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SizedWordRegister rand; // r1: RAND.
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SizedWordRegister tlbl; // r2: TLBL.
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SizedWordRegister bpc; // r3: BPC.
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IopCoreCop0Register_Context context; // r4: Context.
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SizedWordRegister bda; // r5: BDA.
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SizedWordRegister pidmask; // r6: PIDMASK.
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SizedWordRegister dcic; // r7: DCIC.
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SizedWordRegister badv; // r8: BADV.
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SizedWordRegister bdam; // r9: BDAM.
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SizedWordRegister tlbh; // r10: TLBH.
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SizedWordRegister bpcm; // r11: BPCM.
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IopCoreCop0Register_Status status; // r12: Status.
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IopCoreCop0Register_Cause cause; // r13: Cause.
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SizedWordRegister epc; // r14: EPC.
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IopCoreCop0Register_Prid prid; // r15: PRId.
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SizedWordRegister erreg; // r16: ERREG.
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/// Array of COP0 registers.
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SizedWordRegister* registers[Constants::IOP::IOPCore::COP0::NUMBER_REGISTERS];
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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CEREAL_NVP(indx),
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CEREAL_NVP(rand),
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CEREAL_NVP(tlbl),
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CEREAL_NVP(bpc),
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CEREAL_NVP(context),
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CEREAL_NVP(bda),
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CEREAL_NVP(pidmask),
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CEREAL_NVP(dcic),
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CEREAL_NVP(badv),
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CEREAL_NVP(bdam),
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CEREAL_NVP(tlbh),
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CEREAL_NVP(bpcm),
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CEREAL_NVP(status),
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CEREAL_NVP(cause),
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CEREAL_NVP(epc),
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CEREAL_NVP(prid),
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CEREAL_NVP(erreg)
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);
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}
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};
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