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46 lines
1.4 KiB
C++
46 lines
1.4 KiB
C++
#pragma once
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#include "Common/Constants.hpp"
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#include "Common/Types/Mips/BranchDelaySlot.hpp"
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#include "Common/Types/Register/PcRegisters.hpp"
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#include "Common/Types/Register/SizedWordRegister.hpp"
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/// The IOP MIPS R3000 CPU (used as the IOP / PSX CPU).
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/// It uses a little-endian configuration.
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/// There is no official documentation from Sony on any of the IOP - implementation is based off PCSX2's code, and other documents available online.
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/// There are many user-submitted documents about the PSX architecture, which has been used to aid implementation.
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class IopCoreR3000
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{
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public:
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IopCoreR3000();
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/// The 32-bit Program Counter (PC) register.
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/// Points to the current instruction virtual address.
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WordPcRegister pc;
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/// Branch delay slot holding area.
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BranchDelaySlot<> bdelay;
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/// The 32 general purpose registers. They are each 32-bits long.
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/// GPR[0] is hardwired to 0.
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SizedWordRegister gpr[Constants::IOP::IOPCore::R3000::NUMBER_GP_REGISTERS];
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/// The HI and LO registers.
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/// These registers are used to hold the results of integer multiply and divide operations.
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/// They are 32-bit long.
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SizedWordRegister hi;
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SizedWordRegister lo;
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template<class Archive>
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void serialize(Archive & archive)
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{
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archive(
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CEREAL_NVP(pc),
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CEREAL_NVP(bdelay),
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CEREAL_NVP(gpr),
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CEREAL_NVP(hi),
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CEREAL_NVP(lo)
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);
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}
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};
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