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68 lines
2.9 KiB
C
68 lines
2.9 KiB
C
/*
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* Copyright (C) 2010-2024 Fabio Cavallo (aka FHorse)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "input/nes_001.h"
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#include "info.h"
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#include "apu.h"
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#include "clock.h"
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BYTE input_wr_reg_nes_001(BYTE nidx, BYTE value) {
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// in caso di strobe azzero l'indice
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port_funct[PORT1].input_wr(nidx, &value, PORT1);
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port_funct[PORT2].input_wr(nidx, &value, PORT2);
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// restituisco il nuovo valore del $4016
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return (value);
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}
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BYTE input_rd_reg_nes_001(BYTE nidx, BYTE openbus, BYTE nport) {
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BYTE value = 0;
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port_funct[nport].input_rd(nidx, &value, nport, 0);
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// se avviene un DMA del DMC all'inizio
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// dell'istruzione di lettura del registro,
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// avverranno due letture.
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// Aggiornamento da https://www.nesdev.org/wiki/Controller_reading :
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// DPCM conflict
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// Using DPCM sample playback while trying to read the controller can cause
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// problems because of a bug in its hardware implementation.
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// If the DMC DMA is running, and happens to start a read in the same cycle that the CPU
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// is trying to read from $4016 or $4017, the values read will become invalid. Since the address
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// bus will change for one cycle, the shift register will see an extra rising clock edge (a "double clock"),
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// and the shift register will drop a bit out. The program will see this as a bit deletion from the serial
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// data. Not correcting for this results in spurious presses. On the standard controller this is most
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// often seen as a right-press as a trailing 1 bit takes the place of the 8th bit of the report (right).
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// This glitch is fixed in the 2A07 CPU used in the PAL NES.
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// This detail is poorly represented in emulators.[2] Because it is not normally a compatibility issue,
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// many emulators do not simulate this glitch at all.
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if ((machine.type == NTSC) && !info.r4016_dmc_double_read_disabled && (DMC.dma_cycle == 2)) {
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port_funct[nport].input_rd(nidx, &value, nport, 0);
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}
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// NES-001 (front-loading NES) $4016 and $4017, and NES-101 (top-loading NES) $4016 and $4017
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// 7 bit 0
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// ---- ----
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// oooX XZXD
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// |||| ||||
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// |||| |||+- Serial controller data
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// |||+-+-+-- Always 0
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// ||| +--- Open bus on NES-101 $4016; 0 otherwise
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// +++------- Open bus
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return ((openbus & 0xE0) | value);
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}
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