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https://github.com/xemu-project/xemu.git
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hw/sh4: Change debug printfs to traces
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <b776043e811ab3caf200515e1350bdcccd1cc47b.1635541329.git.balaton@eik.bme.hu> [PMD: Fixed format strings for 32-bit hosts] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan
Philippe Mathieu-Daudé
parent
3b885dabd0
commit
ad52cfc137
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@ -31,8 +31,7 @@
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#include "chardev/char-fe.h"
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#include "qapi/error.h"
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#include "qemu/timer.h"
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//#define DEBUG_SERIAL
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#include "trace.h"
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#define SH_SERIAL_FLAG_TEND (1 << 0)
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#define SH_SERIAL_FLAG_TDE (1 << 1)
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@ -89,10 +88,7 @@ static void sh_serial_write(void *opaque, hwaddr offs,
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sh_serial_state *s = opaque;
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unsigned char ch;
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#ifdef DEBUG_SERIAL
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printf("sh_serial: write offs=0x%02x val=0x%02x\n",
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offs, val);
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#endif
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trace_sh_serial_write(size, offs, val);
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switch (offs) {
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case 0x00: /* SMR */
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s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
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@ -301,10 +297,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
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break;
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}
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}
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#ifdef DEBUG_SERIAL
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printf("sh_serial: read offs=0x%02x val=0x%x\n",
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offs, ret);
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#endif
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trace_sh_serial_read(size, offs, ret);
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if (ret & ~((1 << 16) - 1)) {
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fprintf(stderr, "sh_serial: unsupported read from 0x%02"
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@ -101,3 +101,7 @@ exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "UART%d:
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# cadence_uart.c
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cadence_uart_baudrate(unsigned baudrate) "baudrate %u"
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# sh_serial.c
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sh_serial_read(unsigned size, uint64_t offs, uint64_t val) " size %d offs 0x%02" PRIx64 " -> 0x%02" PRIx64
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sh_serial_write(unsigned size, uint64_t offs, uint64_t val) "size %d offs 0x%02" PRIx64 " <- 0x%02" PRIx64
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@ -9,13 +9,12 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/sh4/sh_intc.h"
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#include "hw/irq.h"
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#include "hw/sh4/sh.h"
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//#define DEBUG_INTC
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//#define DEBUG_INTC_SOURCES
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#include "trace.h"
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#define INTC_A7(x) ((x) & 0x1fffffff)
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@ -57,20 +56,14 @@ void sh_intc_toggle_source(struct intc_source *source,
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}
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}
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if (enable_changed || assert_adj || pending_changed) {
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
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source->parent->pending,
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source->asserted,
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source->enable_count,
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source->enable_max,
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source->vect,
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source->asserted ? "asserted " :
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assert_adj ? "deasserted" : "",
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enable_changed == 1 ? "enabled " :
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enable_changed == -1 ? "disabled " : "",
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source->pending ? "pending" : "");
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#endif
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if (enable_changed || assert_adj || pending_changed) {
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trace_sh_intc_sources(source->parent->pending, source->asserted,
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source->enable_count, source->enable_max,
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source->vect, source->asserted ? "asserted " :
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assert_adj ? "deasserted" : "",
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enable_changed == 1 ? "enabled " :
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enable_changed == -1 ? "disabled " : "",
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source->pending ? "pending" : "");
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}
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}
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@ -101,10 +94,7 @@ int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
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struct intc_source *source = desc->sources + i;
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if (source->pending) {
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: (%d) returning interrupt source 0x%x\n",
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desc->pending, source->vect);
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#endif
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trace_sh_intc_pending(desc->pending, source->vect);
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return source->vect;
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}
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}
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@ -199,30 +189,22 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
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return;
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}
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if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: reserved interrupt source %d modified\n", id);
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#endif
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qemu_log_mask(LOG_UNIMP,
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"sh_intc: reserved interrupt source %d modified\n", id);
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return;
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}
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if (source->vect) {
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sh_intc_toggle_source(source, enable ? 1 : -1, 0);
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}
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#ifdef DEBUG_INTC
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else {
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printf("setting interrupt group %d to %d\n", id, !!enable);
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}
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#endif
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if ((is_group || !source->vect) && source->next_enum_id) {
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sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
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}
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#ifdef DEBUG_INTC
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if (!source->vect) {
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printf("setting interrupt group %d to %d - done\n", id, !!enable);
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trace_sh_intc_set(id, !!enable);
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}
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#endif
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}
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static uint64_t sh_intc_read(void *opaque, hwaddr offset,
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@ -235,12 +217,9 @@ static uint64_t sh_intc_read(void *opaque, hwaddr offset,
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unsigned int mode = 0;
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unsigned long *valuep;
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#ifdef DEBUG_INTC
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printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
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#endif
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sh_intc_locate(desc, (unsigned long)offset, &valuep,
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&enum_ids, &first, &width, &mode);
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trace_sh_intc_read(size, (uint64_t)offset, *valuep);
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return *valuep;
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}
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@ -256,13 +235,9 @@ static void sh_intc_write(void *opaque, hwaddr offset,
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unsigned long *valuep;
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unsigned long mask;
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#ifdef DEBUG_INTC
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printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
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#endif
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trace_sh_intc_write(size, (uint64_t)offset, value);
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sh_intc_locate(desc, (unsigned long)offset, &valuep,
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&enum_ids, &first, &width, &mode);
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switch (mode) {
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case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO:
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break;
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@ -282,18 +257,10 @@ static void sh_intc_write(void *opaque, hwaddr offset,
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if ((*valuep & mask) == (value & mask)) {
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continue;
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}
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#if 0
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printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
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k, first, enum_ids[k], (unsigned int)mask);
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#endif
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sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
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}
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*valuep = value;
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#ifdef DEBUG_INTC
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printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
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#endif
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}
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static const MemoryRegionOps sh_intc_ops = {
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@ -416,11 +383,8 @@ void sh_intc_register_sources(struct intc_desc *desc,
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s = sh_intc_source(desc, vect->enum_id);
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if (s) {
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s->vect = vect->vect;
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
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vect->enum_id, s->vect, s->enable_count, s->enable_max);
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#endif
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trace_sh_intc_register("source", vect->enum_id, s->vect,
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s->enable_count, s->enable_max);
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}
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}
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@ -438,11 +402,8 @@ void sh_intc_register_sources(struct intc_desc *desc,
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s = sh_intc_source(desc, gr->enum_ids[k - 1]);
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s->next_enum_id = gr->enum_ids[k];
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}
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: registered group %d (%d/%d)\n",
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gr->enum_id, s->enable_count, s->enable_max);
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#endif
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trace_sh_intc_register("group", gr->enum_id, 0xffff,
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s->enable_count, s->enable_max);
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}
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}
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}
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@ -238,3 +238,11 @@ goldfish_pic_write(void *dev, int idx, unsigned int addr, unsigned int size, uin
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goldfish_pic_reset(void *dev, int idx) "pic: %p goldfish-irq.%d"
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goldfish_pic_realize(void *dev, int idx) "pic: %p goldfish-irq.%d"
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goldfish_pic_instance_init(void *dev) "pic: %p goldfish-irq"
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# sh_intc.c
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sh_intc_sources(int p, int a, int c, int m, unsigned short v, const char *s1, const char *s2, const char *s3) "(%d/%d/%d/%d) interrupt source 0x%x %s%s%s"
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sh_intc_pending(int p, unsigned short v) "(%d) returning interrupt source 0x%x"
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sh_intc_register(const char *s, int id, unsigned short v, int c, int m) "%s %u -> 0x%04x (%d/%d)"
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sh_intc_read(unsigned size, uint64_t offset, unsigned long val) "size %u 0x%" PRIx64 " -> 0x%lx"
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sh_intc_write(unsigned size, uint64_t offset, unsigned long val) "size %u 0x%" PRIx64 " <- 0x%lx"
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sh_intc_set(int id, int enable) "setting interrupt group %d to %d"
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@ -32,6 +32,7 @@
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#include "hw/sh4/sh_intc.h"
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#include "hw/timer/tmu012.h"
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#include "exec/exec-all.h"
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#include "trace.h"
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#define NB_DEVICES 4
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@ -147,15 +148,11 @@ static void porta_changed(SH7750State *s, uint16_t prev)
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uint16_t currenta, changes;
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int i, r = 0;
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#if 0
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fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
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prev, porta_lines(s));
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fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
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#endif
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currenta = porta_lines(s);
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if (currenta == prev) {
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return;
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}
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trace_sh7750_porta(prev, currenta, s->pdtra, s->pctra);
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changes = currenta ^ prev;
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for (i = 0; i < NB_DEVICES; i++) {
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@ -182,6 +179,7 @@ static void portb_changed(SH7750State *s, uint16_t prev)
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if (currentb == prev) {
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return;
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}
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trace_sh7750_portb(prev, currentb, s->pdtrb, s->pctrb);
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changes = currentb ^ prev;
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for (i = 0; i < NB_DEVICES; i++) {
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3
hw/sh4/trace-events
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3
hw/sh4/trace-events
Normal file
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@ -0,0 +1,3 @@
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# sh7750.c
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sh7750_porta(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "porta changed from 0x%04x to 0x%04x\npdtra=0x%04x, pctra=0x%08x"
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sh7750_portb(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "portb changed from 0x%04x to 0x%04x\npdtrb=0x%04x, pctrb=0x%08x"
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1
hw/sh4/trace.h
Normal file
1
hw/sh4/trace.h
Normal file
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@ -0,0 +1 @@
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#include "trace/trace-hw_sh4.h"
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@ -15,8 +15,7 @@
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#include "hw/sh4/sh.h"
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#include "hw/timer/tmu012.h"
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#include "hw/ptimer.h"
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//#define DEBUG_TIMER
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#include "trace.h"
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#define TIMER_TCR_TPSC (7 << 0)
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#define TIMER_TCR_CKEG (3 << 3)
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@ -203,10 +202,7 @@ static void sh_timer_start_stop(void *opaque, int enable)
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{
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sh_timer_state *s = (sh_timer_state *)opaque;
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#ifdef DEBUG_TIMER
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printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
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#endif
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trace_sh_timer_start_stop(enable, s->enabled);
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ptimer_transaction_begin(s->timer);
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if (s->enabled && !enable) {
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ptimer_stop(s->timer);
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@ -216,10 +212,6 @@ static void sh_timer_start_stop(void *opaque, int enable)
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}
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ptimer_transaction_commit(s->timer);
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s->enabled = !!enable;
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#ifdef DEBUG_TIMER
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printf("sh_timer_start_stop done %d\n", s->enabled);
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#endif
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}
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static void sh_timer_tick(void *opaque)
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@ -269,10 +261,7 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset,
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{
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tmu012_state *s = (tmu012_state *)opaque;
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#ifdef DEBUG_TIMER
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printf("tmu012_read 0x%lx\n", (unsigned long) offset);
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#endif
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trace_sh_timer_read(offset);
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if (offset >= 0x20) {
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if (!(s->feat & TMU012_FEAT_3CHAN)) {
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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@ -302,10 +291,7 @@ static void tmu012_write(void *opaque, hwaddr offset,
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{
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tmu012_state *s = (tmu012_state *)opaque;
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#ifdef DEBUG_TIMER
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printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
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#endif
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trace_sh_timer_write(offset, value);
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if (offset >= 0x20) {
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if (!(s->feat & TMU012_FEAT_3CHAN)) {
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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@ -94,3 +94,8 @@ sifive_pwm_set_alarm(uint64_t alarm, uint64_t now) "Setting alarm to: 0x%" PRIx6
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sifive_pwm_interrupt(int num) "Interrupt %d"
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sifive_pwm_read(uint64_t offset) "Read at address: 0x%" PRIx64
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sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at address: 0x%" PRIx64
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# sh_timer.c
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sh_timer_start_stop(int enable, int current) "%d (%d)"
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sh_timer_read(uint64_t offset) "tmu012_read 0x%" PRIx64
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sh_timer_write(uint64_t offset, uint64_t value) "tmu012_write 0x%" PRIx64 " 0x%08" PRIx64
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@ -2459,6 +2459,7 @@ if have_system
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'hw/s390x',
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'hw/scsi',
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'hw/sd',
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'hw/sh4',
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'hw/sparc',
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'hw/sparc64',
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'hw/ssi',
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