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semihosting: Split is_64bit_semihosting per target

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We already have some larger ifdef blocks for ARM and RISCV;
split the function into multiple implementations per arch.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-28 11:31:04 -07:00
parent cd7f29e335
commit ef9c5ea85d
1 changed files with 8 additions and 11 deletions
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19
semihosting/arm-compat-semi.c
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@ -213,6 +213,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr)
return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
}
static inline bool is_64bit_semihosting(CPUArchState *env)
{
return is_a64(env);
}
#endif /* TARGET_ARM */
#ifdef TARGET_RISCV
@ -238,6 +242,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr)
return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
}
static inline bool is_64bit_semihosting(CPUArchState *env)
{
return riscv_cpu_mxl(env) != MXL_RV32;
}
#endif
/*
@ -587,17 +595,6 @@ static const GuestFDFunctions guestfd_fns[] = {
* call if the memory read fails. Eventually we could use a generic
* CPUState helper function here.
*/
static inline bool is_64bit_semihosting(CPUArchState *env)
{
#if defined(TARGET_ARM)
return is_a64(env);
#elif defined(TARGET_RISCV)
return riscv_cpu_mxl(env) != MXL_RV32;
#else
#error un-handled architecture
#endif
}
#define GET_ARG(n) do { \
if (is_64bit_semihosting(env)) { \