Yin Wang 4fc28bf08a hw/riscv: qemu crash when NUMA nodes exceed available CPUs ... Command "qemu-system-riscv64 -machine virt -m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G" would trigger this problem.Backtrace with: #0 0x0000555555b5b1a4 in riscv_numa_get_default_cpu_node_id at ../hw/riscv/numa.c:211 #1 0x00005555558ce510 in machine_numa_finish_cpu_init at ../hw/core/machine.c:1230 #2 0x00005555558ce9d3 in machine_run_board_init at ../hw/core/machine.c:1346 #3 0x0000555555aaedc3 in qemu_init_board at ../softmmu/vl.c:2513 #4 0x0000555555aaf064 in qmp_x_exit_preconfig at ../softmmu/vl.c:2609 #5 0x0000555555ab1916 in qemu_init at ../softmmu/vl.c:3617 #6 0x000055555585463b in main at ../softmmu/main.c:47 This commit fixes the issue by adding parameter checks. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Yin Wang <yin.wang@intel.com> Message-Id: <20230519023758.1759434-1-yin.wang@intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> (cherry picked from commit b9cedbf19cb4be04908a3a623f0f237875483499) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2023-06-14 13:02:36 +03:00
..
boot.c	riscv: re-randomize rng-seed on reboot	2022-10-27 11:34:31 +01:00
Kconfig	hw/riscv: Enable TPM backends	2022-04-29 10:48:48 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals	2022-09-07 09:18:33 +02:00
numa.c	hw/riscv: qemu crash when NUMA nodes exceed available CPUs	2023-06-14 13:02:36 +03:00
opentitan.c	hw/riscv: opentitan: Expose the resetvec as a SoC property	2022-09-27 07:04:38 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
sifive_e.c	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	2022-05-24 10:38:50 +10:00
sifive_u.c	hw/riscv: set machine->fdt in sifive_u_machine_init()	2022-10-17 16:15:10 -03:00
spike.c	hw/riscv: set machine->fdt in spike_board_init()	2022-10-17 16:15:10 -03:00
virt.c	hw/riscv: virt: Enable booting S-mode firmware from pflash	2022-10-14 14:29:50 +10:00