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d9e8553bc8
virt machine is a sim machine with generic PCI host controller. Make common parts of sim machine initialization reusable. Add PCI controller at 0xf0000000 with PIO space at its base address, ECAM space at base address + 1M and MMIO space at base address + 64M. Connect IRQ lines to consecutive CPU external IRQ pins starting from 0. Instantiate network interfaces on virt machine. Xtensa linux kernel configuration virt_defconfig can successfully boot on this machine. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
35 lines
1.7 KiB
C
35 lines
1.7 KiB
C
/*
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* Copyright (c) 2019, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef XTENSA_SIM_H
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#define XTENSA_SIM_H
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XtensaCPU *xtensa_sim_common_init(MachineState *machine);
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void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine);
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#endif
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